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Re: plot log of y axis in cadence
I know that his post is old, but I wanted to get some help desperately. I am using Virtuoso 6.1.5 and want to do exactly what chichi above wants to do. But, I do not see the option 'x axis -> plot vs...' anywhere. I used to do this when I used cadance few...
Hello Sixth,
I am modeling the 5th order CT DS ADC in simulink and wanted to know how did you model the feedback DAC pulse? I have a 1bit switched Cap DAC and am trying to model with a linearly decaying triangular pulse which goes to zero at Ts/2. I am unable to figure out what should be the...
Hi All,
I have been working on CT-DS ADC. It is a single bit quantizer.
From my understanding, say we take NRZ DAC in the feedback and we design the ADC for the DAC amplitude of 1 and DAC width of 1 such that the area of DAC is equal to 1. With the integrator say being 1/s and the sampling...
looks like its a good discussion... thanks every one for your opinion.
What is the general public opinion on middle order analog design companies. Like Marvall, Cirrus Logic, Maxim and some of European giants NXP, STmicro, ST-Ericsson?
How do they stand in analog competency and their future...
Hi All,
I wanted to pick some brain and get people's opinion on how is Intel as far as analog design goes? I mean, in terms of learning and growth. I am a recent college graduate and 've opportunity to join Intel and my area of interest in analog and mixed signal design field. I understand...
Re: matlab FFT problem
attached in matlab code.
%Script for Question two in Assignment 3 of VLSI data conversion circuit
%Deals with finding the peak quantization noise ratio for various
%resolutions.
%% Define the input signal
clc; clear;
p=10;
Nfft = 2^p;
n = 0:1:Nfft-1; % taking Nfft...
Hi All,
I am trying to quantize a sinusoid signal and then plot its FFT using matlab.
I did the quantization as in the attached file and then took the FFT.
If you see, the FFT is not quite convincing. I mean, not in terms of SNR/SFDR but if you see the bottom of the fft, it looks like it...
HI All,
I am trying to find SQNR using a matlab code i wrote. But i am not sure where am i mistaking as the result is not matching to the standard equation of SQNR = 6.02N + 1.76.
attached is the matlab code.
%% Define the input signal
clc; clear;
p=10;
Nfft = 2^p;
n = 0:1:Nfft-1; % taking...
Re: Mismatch analysis
HI Keith,
I was once again looking at analyzing the offset and i have this small doubt.
For the offset considerations, i considered M1/M2 pair and M3/M4 pair. Now, I am not sure that shell i take M3/M5 and M4/M6 pair or M5/M6 pair or all the of them?
I guess i should...
Re: Mismatch analysis
Hi Keith,
Yeah, i want to find the offset due to mismatch in each pair of transistor and i was pretty much able to do that for all the other pair but for M3/M4. ( I also took M3/M5 as a pair)
But, i would again request you to please clarify on my question about the...
Re: Mismatch analysis
Hi,
Systematic offset measurement:
1. I didn't get you when you say 'put maximum vth difference on to the transistors'
2. Also, what do you mean when you say 'applying multiple offsets'. I believe i am not applying any offset from outside.
(just to make it better...
Re: Mismatch analysis
Hi Keith,
Thanks for the clarification. That was helpful.
At the same time, if i want to simulate the same circuit for systematic offset (not random offset), how should i go about doing it. This is a comparator and not opamp, so i believe i need to have some trick.
What...
Re: Mismatch analysis
hi,
I think what i am trying to say is, if i add the small voltage , say in series with the source of M3, that will come in between vdd and source right.
so,now the equation for current in M3 would become = kw/2l (vdd-vn-vth)^2
then i have following doubts:
1. is this...
Re: Mismatch analysis
yeah, i did that. like added a small voltage source at the gate of load transistors.
I was wondering, should i be doing small signal analysis (hand calculation) or large signal.
What i mean is, after putting a voltage source at the gate, should i consider the vdd to be...
Hi,
In the figure below, I want to model the mismatch in M3/M4 device. (like may be say Vt mismatch)
I know how to do that for M1/M2, M3/M5 and M7/M8 pairs but how shell i do for M3/M4 pair.
thanks
noise at the output:
HI all,
I have a track and hold followed by a source follower buffer (on silicon) and i have been testing it and seeing the output on an oscilloscope. Attached in one of the outputs i see. It has input signal of 100MHz and sampling frequency is 20MHz ( it is sub-sampling...
HI all,
I have a small question which i am getting confused with,
I am testing a track and hold (on silicon) and want to see the spectrum of output on a spectrum analyzer. But, unlike a sample and hold , the track portion of the output would end up messing things up , i guess. I feel that i...
Re: FFT computation.
hi,
yeah , i understood that, but i have one more question then,
when we take fft, we maintain the ration of fin to fs equal to m/M where m and M are coprime numbers with M = 2^n.
so now say that my system is for subsampling, and fs = 20Mhz and i need input to be...
Re: FFT computation.
HI,
Yeah, i understand the relation of input frequency and sampling frequency being:
Fin/Fs = n/M , and also the reason for n being odd/prime. But when you say i have to lock the signal source with clock generator using 10Mhz sync at the back of the boxes , where do you...
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