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    What is meant by macromodeling of power?

    What is meant by macromodeling of power. How does it differ from micro modeling. Pl. help me with an example
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    What is the difference between micromodeling and macromodeling ?

    Hi All, What is meant by power macromodeling in digital circuits What is the difference between micromodeling and macromodeling ?
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    Need link to MCNC benchmark circuits

    Hi All, Please help me to get the tar ball or www link of MCNC benchmark circuits. The link specified in literature (www.cbl.ncsu.edu/CBL_Docs/Bench.htm) for the same is not working. kindly help me
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    in a CMOS circuit, what is meant by drive strength ?

    in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors affecting drive...
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    What is meant by drive strength?

    Hi All, In a TSMC cell like AOI221X1 what is meant by drive strength ? Pl. give me a detailed explanation of the same
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    I can bring workspace switcher to control panel

    workspace switcher I am using fc4 and suddenly all desktop settings changed and all my control panel setting changed. Now I am unable to bring workspace switcher in to control panel. Kindly help me to solve this. with thanks
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    Need free software for converting edif to verilog

    Is there any free conversion utility to convert edif description to verilog? Pl. help me in this regard
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    switching transition count

    For given large combinational or sequentail gate level circuit, how can I calculate total switching transitions (0->1 and 1->0) provided that two input vectors in sequence. Kindly suggest one efficient idea so that I can implement it effectively
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    Latex error concerning beamer class

    I have installed beamer class as root and class fiel are stored in the directory /usr/share/texmf/tex/latex/beamer/base. But while I am trying to run one simple tex program it is showing error as shown below. ash-3.00$ latex test.tex This is TeX, Version 3.14159 (Web2C 7.4.5) (./test.tex...
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    Question about analyzing gate delays

    Re: gate delay In order to justify the concept, I calculated the AND gate delays (50%) for 130,90,65 and 45nm tech... in eldo. The result is given below , but this values are not correlating properly. Could you please cpmment on it ? 130nm 53.7ps 90 52.6ns 65 81.05ps 45...
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    Question about analyzing gate delays

    gate delay Hi All, I have a basic doubt in gate delays. When we analyze the gate delay of and gate in 90nm , 65nm and 45nm technology which one is more. Pl. give me proper exlanation and justification for the same
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    rcx extraction problem in 90nm technology

    spice gate delay Hi, Ur explanation is lcear for me. But this delay and EDA tool delay calculaion need not be same. Anyway I will try with spice. BTW do you have any idea abt the interconnect delay analysis using spice. There r transmission line model in spice but will it be suitable for...
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    What does "wrapper" stand for ?

    Another very good example for wrapper application is asynhronous synhronous domain mix in a design. Or when we design a GALS besd system we have to think about wrappers.
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    rcx extraction problem in 90nm technology

    90nm spice Sorry for the confusion. I will explain my problem in a detailed manner. We have magma tool eith 130nm TSMC libarry. But i have to calculate the delay of one deoder circuit for 90nm technology. If I kbnow the gate then I can calculate the Total delay of the circuit. So is there any...
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    output generation in verilog

    Pl. refer Verilog book by Samir palnitkar. All these concepts are clearly explained in this book
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    interconnect delay minimization

    Hi Why cant u post the question in poper way. It is too bad to post question by simply cut and paste. Atleast U should see it once before posting.
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    Tcl used in Modelsim?

    Hi mentor graphics provides excelelnt support for this. In the example directory there is special directory called tcl_tutorial/ which explains this concept. Added after 13 minutes: Hi mentor graphics provides excelelnt support for this. In the example directory there is special...
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    How to use Eldo/ Spice for energy analysis?

    Re: spice analysis There is no difference in using spice and pattern. U can use .MEAS statement to measure power and from there u can calcualte energy
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    iscas 85 benchmark circuits

    iscas 85 benchmarks U can generate it very easly using perl script. It is a matetr of small program in perl. First of all u have to to make all subckt library for basic gates and use thise subcircuits to replace the basic gates in iscas circuits.
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    How to use Perl while coding in Verilog?

    Re: perl U can try like this in ur perl code. system ("/tools/ams/bin/eldo temp.cir"); Here I am assuming eldo as the tool name

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