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  1. S


    recently, i saw there was one written style as the title. this command line was written in one sequence. As everyone knows, sequence is an ovm_object, so it can not use get_config_object directly. but i still do not know what does p_sequencer.get_config_object mean, where could this sequence...
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    why there is no real sequencer, only virtual sequencer for this sequence. OVM

    Hi All, I have a question for below code for OVM class base_vseqr extends ovm_virtual_sequencer; X_seqr X_seqr_h; Y_seqr Y_seqr_h; `ovm_sequencer_utils(base_vseqr) ..... endclass class A_seq extends ovm_sequence; B_seq B_seq_h; `ovm_create_on(B_seq_h, p_sequencer)...
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    what's the difference between BRANCH and COND in coverage simulation in VCS?

    In VCS userguide, when doing coverage simulation, COND means condition coverage, BRANCH means branch coverage. As the report shows, COND coverage simulation will underline condition statement like "if (A==0)" and BRANCH coverage simulation will underline branch "QUESTION MARK" in statement like...
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    Master with tapeout exerience, looking for Digital IC related job in Singapore

    Hi, everyone, I'm a master in China, major in Digital IC field. I have four years experience in digital design since undergraduate term. I have hands on experience in tape-out (.13 technology) and familier with front to backend digital ic design flow. Besides, I have experience in FPGA...
  5. S

    why negative hold time?

    thx to above answers. it seems possible that the intrinsic hold time is negative just because the inner combinational logic. Is that alright?
  6. S

    set_input_delay means ?

    Thank U for ur explanation
  7. S

    set_input_delay means ?

    Hi guys, I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design...
  8. S

    what does set_input_delay mean?

    Some thought it means the delay from the signal source to the first register in the core design. But according to <ASIC timing verification> book, it seems that it means the delay from the signal source to the first stage circuit (no matter register or gate) in the core design. These two...
  9. S

    balsa user: how to implement multiplication in balsa

    when I'm trying to multiply A by 2, it seems there is no pre-defined macro in balsa. Thus, I'm trying to use shift method to implement multiplication as below: variable A : 8 bits type A8 is array 8 of bit type B8 is 8 bits B := (A8 {0}@{(#A)[0:6] as B8}) but there is an error message...
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    Incorrect pid lock detected and removed (/root/.breeze-sim-ctrl/2848)

    when use balsa to simulate, here lays the error report. I cannot open GTKwave, but I've already installed gtk. PS: I'm under ubuntu 10.04 OS anyone met this problem????
  11. S

    when breeze2ps, error happens. help balsa users

    |_ ._ _ _ __ _ ')._ _ [ breeze2ps: Breeze -> Postscript Converter ] |_)| `(-'(-' /_(-'/_|_)_/ (C) 2000-2008, The University of Manchester | ERROR: In procedure scm_i_lreadparen: ERROR: test:15:1: end of file
  12. S

    Asynchronous circuits synthesis tools

    any place can find Balsa software??? is this software an independent one or it is a suit?

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