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  1. S

    MTBF MIL217 Quality

    Thanks for replying. Yes I agree it's becoming really hard to find information. I'm just trying to understand how Mil spec quality factor D, C, S, B, R, P, M etc relate to commercial components. I know there are lots of different method and spec, much newer, is there a better one I should be...
  2. S

    MTBF MIL217 Quality

    Hi I'm evaluating the MTBF for a relatively new smd electronic design. It's not something I've really done before myself. So I've been going through the MIL-217 reliability spec, and evaluating some software and online calculators. I thought I'd start with the component 'count' type then...
  3. S

    PCB design for ATEX.

    Hi Thanks for answering. This is my first certified product. Not an easy task I'm finding out. The board I'm working on is fitted in a box before encapsulating. We leave a 3mm gap between PCB edge and the internal box wall. So the PCB is completely surround by potting compound I found out...
  4. S

    PCB design for ATEX.

    I'm wondering if I can get some help interpreting a part of the ATEX standard (IEC 60079-18)? I am designing a PCB for ATEX certifcation, encapsulated type 'mb'. Under 7.4.3.2 'minimum distances' (page 23-24) there is a table (5) and diagram (figure 2) of the PCB stack-up. In my case, from...
  5. S

    Calculation of Potting compound thermal resistance

    Hi Could someone please help me with a problem. I have a PCB that fits in an ABS box and is to be completely potted, top and bottom. I am investigating device failure modes, as I need to ensure that the outside surface temperature does not reach 135C. I've worked out that one SOT23 device may...
  6. S

    VHDL Possible timing problem?

    Hi This block is part of a slight larger FPGA circuit, though the rest of the circuit is very simple. It just takes in lots of inputs (around 48) from the FPGA pins, deglitches them, then ORs them together to create tx_data_bus. In term of simulation, I use Modelsim. I created some stimulus...
  7. S

    VHDL Possible timing problem?

    Hi, I'm relatively new to VHDL and I wonder if someone could have a look through this bit of vhdl code. The FPGA is a A42MX09, the IDE is libero. I have simulated the code, before and after synthesis and it appears fine. Synthesis does not show any errors. Basically it's a serial data stream...
  8. S

    Inner layer track distances

    Yes I agree with what you say, I wish it was clearer. I'm wading through the standards and it's not straight forward. They don't appear to be written by people who use them. I'm undecided what to do at the moment, I think the distance I can achieve would be ok (1,8mm, maybe more). If I fit...
  9. S

    Inner layer track distances

    I've managed to see IEC61010-1 3rd edition. Sections 6.7.2.2.3. There's also table K1.3.3 (Inner insulation layers of printed wiring boards) Yes I can see that 0.4mm is the minimum distance between two adjacent conductors. However, there's a note a these values are independent of the overvoltage...
  10. S

    Inner layer track distances

    Ok Thanks for the all your efforts I really appreciate it. I will see if I can get EN 61010-1. I am looking at ECMA-287 as well which was mentioned before As you say, this is not very clear at all. Looking at the PCB the maximum inner clearance between Live and earth tracks etc, I will be...
  11. S

    Inner layer track distances

    Beyond 500V peak it uses a simple formula for inner layers. 0.25mm + 0.0025mm/Volt x (voltage above 500V) So for 1KV the inner layer distance would be 0.25mm +0.0025mm/v x 500v = 1.5mm What other standards have you seen? or I could refer to?
  12. S

    Inner layer track distances

    Hi Interesting. I should say standard. This is really what I want to check. I am looking at the IPC-2221A electrical clearance table, though not the latest copy. I have been searching the internet and I see 0.25mm as a common figure. I am not intending to have Live, earth and Neutral cross...
  13. S

    Inner layer track distances

    Hi I am working on a PCB which is going to work at 240Vac mains. I am struggling with creepage and clearance distances, so the only answer I can see is to put the mains Live and neutral on inner layers. I have looked at the spec and see that the clearances for an inner layer will be >0.25mm...
  14. S

    Solder resist breakdown voltage

    Thanks for answering Yes, this is what I thought. I read a paper which suggested otherwise which is why I asked.
  15. S

    Solder resist breakdown voltage

    Hi I wonder if someone could help with this question. What is the breakdown voltage of solder resist. I have seen a value of 500V-1000V/mil. So can solder resist be relied on to reduce the track distance between 240V mains live, neutral and earth. If so what would be the minimum track...
  16. S

    Cable attenuation / input impedance

    Hi Sorry for not being clear, (I used the wrong symbol name should be 'Γ') RhoL was the load or teminating reflection coefficient. = (RL - Zo) / (RL +Zo) RhoS was the source reflection coefficient. = (Rs - Zo) / (Rs +Zo) I'm happy it works for a single lossy line. I'm looking at it for a...
  17. S

    Cable attenuation / input impedance

    Hi Thanks Yes I have been using simulator to analyse the transmission line I am working on. The real circuit is quite alot more complicated, I prefer to understand what is going on before trusting it. I think at the frequency I am looking at the skin and proximity effect multiplies the cable...
  18. S

    Cable attenuation / input impedance

    Yes cable inductance L in uF/m is a typo error. Should be 1uH/m, so 1mH over 1km. and yes characteristic impedance is 100ohms. Thanks
  19. S

    Cable attenuation / input impedance

    Hi Thanks for answering I managed to derive and calculate the propagation values, α and β. I know what the resistance and inductance will be due to skin and proximity effect etc. So, if the cable is not matched how do you work out the input impedance for a lossy line, for a particular...

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