Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
can anyone tell me how to select set up time, hold time , rise time , fall time.
is it depend on the frequency of the design or the technology library
do we need to give transition time for the output pins also
waiting for reply
Sample ASIC Design flow
can anyone tell me good website which provide me sample netlist to asic design flow, so that i can do only P & R, is there any sample verification modules , which talks abt verification plan , test plan , test cases
waiting for good reply
ASIC with MAGMA
does anyone tell how far this tool is better than other tools like cadence any synopsys.
can anyone tell wht is best feature in magma
and why it is advantageous than others
how far it cope up with low power vlsi