# Search results

Hi all I have a puzzle when using the Sigmadelta ADC design tools by Richard Schreier. For the function of SynthesizeNTF, with a argument of 'H_inf', which is the maximun out-of-band gain of NTF. For 1-bit, maybe Lee-rues can used, that H_inf=1.5; While for multi-bits, How to set the value of...
2. ### I need a paper, who can send to me?

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers Hurst, P.J.; Lewis, S.H.; Keane, J.P.; Aram, F.; Dyer, K.C.; Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA This paper appears in: Circuits and Systems I...

Hi everyone I met a question in the designing the mash sigmadelta adc. In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade sigma delta adc for sensor and telecom). I have finished the schematic, and is doing the spectre...
4. ### About the Balun application!

Hi I use the balun to transfer the single signal to two differential signals. But i met a problemn. When i input a 1M sinewave, the differential signals are ok. When the input signal frequency increase to beyond 5M, the output differential signals are almost the same, not differential...
5. ### Question:Input Offset voltage of OPAMP of S/H of pipeline AD

op amp input offset Hi guys I have a question about the pipeline adc. In behaviour model of pipeline adc, every issue is ideal except the OPAMP offset voltage of OPAMP in SH. When i set the offset voltage of opamp in SH 2mV, the enob is about 8.8bit (9.9bit at all ideal issue). Here i am...
6. ### Question about the PSRR the frequency range

About the PSRR Hi all a puzzle about the psrr. When we consider the PSRR of ompap or bg, what is the frequency range we should be attention? 0~1M is ok? why? Thanks Donghui
7. ### About the relationship between pole/zero and settling time

Hi all I am designing a Sample hold opamp with cascode compensation. I have known the opamp has a pole and a zero very near. So in order to decrease the influence on settling time of doublet, i push this doublet far away from the loop BW(about 3*BW), And other high fre poles and zeroes are all...
8. ### a problemn of ADC simulation with Hspice.

hspice adc snr Hi all I use the HSPICE to simulate the whole pipeline adc. I want to check its SNR. So i run the tran. simulation with 2048 points, then transfer the .tr0 file to matlab to fft to get the snr value. If i use 0.01ns transient step in tran simulation, the fft results is about...
9. ### a question of the noise simulation with hspice

HI all I want to simulate the noise of an OPAMP with Hspice. From the log file, i can see such as the following at one frequency! element 5:mi151 5:mi123 5:mi150 5:mi100 5:mi156 rd 0. 0. 0. 0. 0. rs 0. 0. 0. 0. 0. id 1.339e-26 4.355e-28 7.686e-26 0. 0. rx 130.6988m 15.2482m 120.2688m 1.3594u...
10. ### a question about the noise simulation with Hspice

HI all I want to simulate the noise of an OPAMP with Hspice. From the log file, i can see such as the following at one frequency! element 5:mi151 5:mi123 5:mi150 5:mi100 5:mi156 rd 0. 0. 0. 0. 0. rs...

adc snr HI all i am simulation a pipeline adc. I give a sine input, and do .tran simulation in hspice. Then catch the 10-bit digital code to do fft in matlab. Then i want to know, the fft results can give the SNR results? And is the noise compont included in the tran simulation results...

thomas cho berkeley In the phd paper of Thomas cho's ADC, page 100. He said large error correction range can eliminate the dedicated input S/H circuit. And the input signal can be sampled simutaneously by switched capacitor amp and dynamic comparatorof flash A/D. How to understand this...
13. ### About the tools to compile and simulate the Verilog-A ?

Can someone suggests some easy tools to compile and simulate the verilog-A. Thanks!
14. ### About the INL and DNL test of 11-bit pipeline ADC!

HI all I am testing a 11-bit ADC INL and DNL. I have read the maxim histogram test app note. But I have some questions about the test setup. 1) For 11-bit and 27MHz sample clock, how to add the input sinwave signal. what the frequency of the sinewave signal. How can i guantee...
15. ### About the PSRR frequency range!

HI all I have a puzzle about the PSRR frequency range. For normal analog block, such as OPAMP, BG, when we consider its psrr, how is the power ripple frequency range is considered. 1K is enough? I thought on the chip( and also board), a big cap is between the power and ground. So...

T. Miki, Y. Nakamura, K. Okada, and Y. Horiba, “Transient analysis of switched current source,” IEICE Trans. Electron., vol. E75-C, pp. 288–296, Mar. 1992.
17. ### how to test the INL and DNL of DAC?

I have designed a 10-bit DAC. Through the transist simulation ,i have the results of output waveform( analog output vs input digital data). But i want to know how to extract the INL and DNL from the transist simulation results? Matlab? Can someone share the material. Thank you very...
18. ### how to design a high gain, bandwith, swing out opam!

I am designing a opam with 70-80db gain, and more than 20MHz bandwidth, and real-to-real output. Can some one give me some suggestions about the structures? THANKS GDHP
19. ### for dac layout: current source switching sequence

i am designing a 10-bit dac ,whichi is 5+5. For 32 MSB, i want to use the double Centroid Switching scheme. can some one give me some suggesiton about the double Centroid Switching scheme.? what is the detail? thank you!
20. ### how to simulate the INL and DNL, SFDR in hspice?

I'm design 10-bit DAC. How can i simulate the INL and DNL ,SFDR in hspice? Or is there other tools to simulate it? Who can tell me the detail? Thanks gdhp