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  1. N

    how to run analysis of OP Amp(low power)

    I can't understand what do you mean by the input offset voltage!! can you explain more? What is the source of this offset? I still think that after correcting the output node, the description in my first and second replies should be followed.
  2. N

    different transient and ac analysis results

    I am accurate enough. I think the problem is about the non-linearity.
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    TSMC MIM capacitor array layout problem

    As I know there is no relation between CTMDMY layar and Density error of DRC!!! CTMDMY (capacitor top metal dummy layar) is a dummy layer to specify your capacitor area, which is useful in LVS process. The density DRC error is an error which is occure when the density of a metal is less than a...
  4. N

    Input Commom Mode voltage: Switched Capacitor circuits

    It may act in that period of time as a buffer, helping to store the input or output signal on a capacitor.
  5. N

    how to run analysis of OP Amp(low power)

    Agree with DenisMark! Follow the signal path!!!
  6. N

    how to run analysis of OP Amp(low power)

    Also: 1- choose the resistance value as large as possible, not to affect on the OTA ac operation. 2- Use a large capacitor from the negative input of the OTA to ground, to zero the ac value of this pin.
  7. N

    how to run analysis of OP Amp(low power)

    For testing such an OTA with differential input and single output, you should know the input and output common-mode voltages for which the OTA is designed for. Also you need to design a test-bench circuit and use this OTA in a feedback loop, which sets the output common-mode voltage of the OTA...
  8. N

    different transient and ac analysis results

    How should I measure the cutoff frequencies after fabrication? Shouldn't I use a procedure similar to the transient analysis? If I do the design based on the ac analysis, would I have proper characteristics after fabrication?
  9. N

    different transient and ac analysis results

    I have applied a very small amplitude signal to the input of the amplifier, but the results from ac and transient for the low-cutoff frequency are different yet. for example, from the ac analysis the low-cutoff frequency is around 10 Hz and the gain of the amplifier in this frequency is 370. But...
  10. N

    different transient and ac analysis results

    I have find the low-cutoff frequency by 0.7 * (maximum gain) approximately. - For the first point: The DC analysis shows desired results, also I tried to set some important nodes voltages of the amplifier, but no changes in the results. Is there any option to specify one point of my transient...
  11. N

    different transient and ac analysis results

    Hi I have simulated an amplifier using spectre. But when I want to calculate the low-cutoff frequency of the amplifier, it seems that the transient and ac analysis shows different responses. What is the problem? Is it about the simulation settings?
  12. N

    post layout simulation using spectre

    Hi I know how I can extract my layout using calibre. My first question is that what should be the format of extracted netlist (calibreview, ELDO, Spectre, ....) if I want to do my post layout simulation using spectre? Also I want to know how should I do post layout simulation or how can I make...
  13. N

    process variation in advanced technologies

    But what about the coefficient of 1/sqrt(W.L)???? if we assume two same dimension transistors? Actually I want to know what happens to dVt and dB (beta) parameters. Are these increase or decrease by improving technology??
  14. N

    process variation in advanced technologies

    Can you please give me a reference???
  15. N

    process variation in advanced technologies

    Is the absolute and relative variation of process increased in advanced technologies or not? Does the answer is different if the technology assign for minimum energy sub-Vt circuits? In analog design, it says that the matching of elements improve in advanced technologies. Does it mean that the...
  16. N

    references on sub-threshold logic design

    Can any one refer me some good references on design and implementation of Flip-Flops, XOR and MUX in subthreshold?
  17. N

    ADC dynamic parameters test

    Hi I want to plot SNDR versus an other parameter and I want to know for what input amplitude I should simulate the ADC? Which SNDR is more important for us? the maximum SNDR or the SNDR for full-scale input?
  18. N

    ADC dynamic parameters test

    Hi In testing the SNDR specification for an analog to digital converter, how can we choose the input signal amplitude, if the input dynamic range is limited? should the input signal amplitude force to the full-scale anyway, or it can be reduced, achieving a better dynamic specification?
  19. N

    Issue about testing lumped JFET devices

    Lumped JFET test I think the diode mode of the multimeter is showing the junction ON voltage, for example a voltage between 0.5 to 0.7 V. My question is that, why are the voltages different according to the symmetry of the JFET structure?
  20. N

    Issue about testing lumped JFET devices

    Why in lumped JFET devices, testing with diode mode of multimeter, the gate-source junction shows higher voltage than the gate-drain junction?

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