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  1. Z

    sizing cascode transistor

    for NMOS pair, bottom mirror should have larger L to obtain good matching. the top pair are used to enlarge the output impedance
  2. Z

    question of comparator

    to get the min. delay, for fixed taper factor inverter chain, the scale factor of inverter is e, 2.718, so, people sometimes use 3, also, 3 or 4 are similar reason, and factor 4=2^2 is easy to calculate. also, using factor 4 can save one or two stages if the driver chain is long, in that case...
  3. Z

    A strange phenominon about current mirror

    I think for current mirror, channel length should be longer to reduce CLM effect. Also, for large conversion ratio, large current side has lower Rdson, if it can not be large enough to satisfy the ideal current source assumption (with infinite rds), it will have impact.
  4. Z


    source biasing mos in real fact. all mos are 4 terminal devices. generally, there are 2 operating. (use nmos for example) 1. source and bulk(substrate or pwell) connect together. based on standard cmos process, there are not isolated P-well, so, bulk is directly connected to substrate together...
  5. Z

    How to level shift a voltage by Vthn0?

    thanks vbhupendra. yes, by using SF, voltage can be shift up by Vgs or several Vgs, but one problem, how to avoid the body effect. conventional process donot support isolated p-well, i think that is a problem.
  6. Z

    How to level shift a voltage by Vthn0?

    I want to level shift one voltage Vin up by one Vthn0 (threshold voltage of NMOS when Vgs=0), I am not sure how to use NMOS to realize it? Thank you very much!
  7. Z

    Can i use MOS capacitor to implement compensation?

    yes, you can. and make sure that one port of cap(connect to bulk) should be connected to Vdd or GND.
  8. Z

    Where did the energy from the capacitor go?

    Re: Where did the energe go?

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