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to get the min. delay, for fixed taper factor inverter chain, the scale factor of inverter is e, 2.718, so, people sometimes use 3, also, 3 or 4 are similar reason, and factor 4=2^2 is easy to calculate. also, using factor 4 can save one or two stages if the driver chain is long, in that case...
I think for current mirror, channel length should be longer to reduce CLM effect. Also, for large conversion ratio, large current side has lower Rdson, if it can not be large enough to satisfy the ideal current source assumption (with infinite rds), it will have impact.
source biasing mos
in real fact. all mos are 4 terminal devices. generally, there are 2 operating.
(use nmos for example)
1. source and bulk(substrate or pwell) connect together. based on standard cmos process, there are not isolated P-well, so, bulk is directly connected to substrate together...
thanks vbhupendra. yes, by using SF, voltage can be shift up by Vgs or several Vgs, but one problem, how to avoid the body effect. conventional process donot support isolated p-well, i think that is a problem.