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  1. S

    DCT - two simple conceptual questions

    DCT Hi, I am new to signal processing and currently trying to understand the DCT concept. There are mainly 2 conceptual questions I have: 1) the dct equation is given as: Xk = summation (xn cos ....) Which can be expanded as: x0 = x0 cos (0) + x1 cos (..) + x2 ... Similarly x0 Here a)...
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    Applying IO standards that do not use CMOS transistors

    iostandard jedec Most of the IO standard names, I do agree. But TTL has traditionally been used to mean BJT transistors. So I am thinking what the standard committee had in mind when they named LVTTL, when it is well known that such IO characteristics needs to be provided by other transistor...
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    C-Based Verification Environment

    Hi Paul, In my experience, I have always seen requirement to use a HDL along with C to create a verification environment. How much you would want to accomplish in C and how much in HDL varies. In C+Verilog environment, the timing aspects are modeled in verilog and things like dynamic memory...
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    CObinatinal feedback loop

    Jaydeep, when Paul says timing advantage, he means that at places combo feedback is used to avoid having to wait for 1 cycle to take a decision. At such places, you put feedback to get 1 cycle timing advantage. I am not able to recall an example, but vaguely remember that in processors if w/o...
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    CObinatinal feedback loop

    Paul, processors probably have one of the most stringent timing budgets, but that would be an exception rather than a rule. Another interesting observation I have seen previously is simulator going in infinite loop (time not moving) due to combo loopback in the designs. Basically the update...
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    Applying IO standards that do not use CMOS transistors

    jesd8c I am not sure if I communicated well enough ... Basically I am talking about few IO standards which obviously seem to use non-cmos logic. One such example is LVTTL. We know that TTL uses BJT as the underlying transistors (thats what classical description for TTL logic shows). We also...
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    Has any one used save/resotre to speed up the simulation?

    Re: save/restore Save restore per-se does not speed up the simulation but is used to take a snapshot of a simulation data at a particular instance and then re-start it from there. What could be the advantage of doing that: one useful advantage of this is that one can pass parameters to the...
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    looking for information on circuit reset schemes with FPGAs

    reset scheme Hi, Anyone know about a good links to reset schemes. Especially looking for information on circuit reset schemes that contain FPGAs since the reset should be active until FPGAs are configured. Regards,
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    Applying IO standards that do not use CMOS transistors

    io standards Actually my question was a bit generic while you picked up a specific example and answered. So let me rephrase - Most of the FPGAs actually support almost all the IO standard types available. So can I assume that these are all designed using CMOS? Also, some of the IO standards...
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    Applying IO standards that do not use CMOS transistors

    Hi, Some of the IO standards (e.g. CML) actually do not use CMOS transistors inside their IO buffers. Since most of the FPGAs are follow CMOS technology and they also support these IO standards, how are these actually supported? Of course, the same question would apply even to ASICs also...
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    jtag: analog/mixed signal ics

    Hi, I was looking into datasheets of some analog and mixed signal ICs and they dont contain any jtag port. So is it generally the case that analog ICs are left out of jtag chain. Also, why not have a jtag port and include them since that would make board testing so much simpler? Regards,
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    very low speed clock: i2c, uart

    Hi, Can anyone tell me how low speed clocks are derived in i2c or uart applications. As I understand these cores typically operate at core frequencies which could be 50Mhz upwards. Specifically I have the following questions: 1) Does most of the cores (i2c core) operate at core frequency and...
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    clock division - using analog logic, logic in the clock path

    Re: clock division True that gates clocks add additional skews. But that is also the case in ASIC. But the issue seems to be more than that in case of FPGAs due to which I have seen recommendations not use gated clocks. Regards,
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    clock division - using analog logic, logic in the clock path

    what do divisions mean on a clock Hi, I have couple of questions pertaining to clocks 1) why is it necessary that one uses analog logic like pll to do a clock division when it can be done using just flops 2) why fpga technology prohibits logic in the clock path e.g. to gate the clocks Regards,
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    CAM question about match / no_match

    Hi, I am going through a xilinx app note. The basic CAM that is shown is a 32X9 capacity. The total memory capacity used up to implement this is 16kb. I am wondering if the idea is to generate just a match or no_match then just a 512 bit single bit memory array would do the job. Where the array...
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    Why independent clock is fed separately to SERDES?

    I am looking at a legacy design. The design accepts 2 clocks (of same frequency and from same source), one goes to core logic and other goes to SERDES block. I am not sure why an indepdent clock is fed separately to SERDES while the same core clock can be used. When I refered to design document...
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    What does the ASIC NRE cost consist of ?

    Can someone tell me what does the ASIC NRE cost consist of ?

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