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  1. D

    size of sram pull up transistors

    I have read some where that the pull up transistors should be weak...why is it so?
  2. D

    SRAM layout question - which metal layers ?

    SRAM layout question In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
  3. D

    Interview question about a FIFO depth

    i have a question that is asked in an interview . i am writing into fifo asynchronously with 25 writes per second and reading form fifo with 25 reads per second synchronously. then what the depth of this fifo? My answer is no fifo required..am I correct?if not please explain the right ans
  4. D

    unsigned numbers question

    Suppose A,B,C are unsigned 32-bit numbers. How many bits are needed for Y = (A*B) + C?
  5. D

    hold time dbt - need explanation of a sentence

    hold time dbt Can some body plz explain the following to me : because the launch edge and the capture edge is the same edge, the hold timing check doesn't depend on the clock period. how can launch edge and capture edge be the same for hold time?
  6. D

    clock jitter and hold time

    jitter hold setup I read some where that clock jitter does not effect hold time violation..is it true?if yes then why?
  7. D

    capacitance between interconnect

    HI, I come across this question at several places but never got the right answer: there are 3 parallel layers of metal interconnect and all three of them are switching as below: case1:the middle interconnect is switching in one direction(say 0 to 1) and the outer 2 interconnects are BOTH...
  8. D

    capaticance between interconnect

    capaticance HI, I come across this question at several places but never got the right answer: there are 3 parallel layers of metal interconnect and all three of them are switching as below: case1:the middle interconnect is switching in one direction(say 0 to 1) and the outer 2 interconnects...
  9. D

    fundamental of digital circuits

    Where can I download Fundamental of digital circuits by A.Anand ebook. I need it urgently for an interview.
  10. D

    Fundamental of digital circuits

    fundamental of digital circuit Where can I download Fundamental of digital circuits by A.Anand ebook. I need it urgently for an interview.
  11. D

    why is inductance not considered?

    y is inductance not considered anywhere in digital design(layout,delay estimation,etc)?
  12. D

    what is the use of epi layer in CMOS IC manufacturing?

    epi-layer? what is the use of epi layer in CMOS IC manufacturing?
  13. D

    sequence detector FSM design

    sequence detector fsm Q. Design a Pattern matching block - Output is asserted if pattern "101" is detected in last 4 inputs. - How will you modify this design if it is required to detect same "101" pattern anywhere in last 8 samples?
  14. D

    even or odd number of fingers?

    why is using even number of fingers better than using odd number of fingers in large transistor layout design?
  15. D

    f u use stacked vias,the parasitic capacitance will reduce?

    stacked structures? is it true that if u use stacked vias,the overall parasitic capacitance will reduce? and why are many small contacts preferred over one big contact?
  16. D

    what is metal fill lines connected to?

    I know what a metal fill is and why it is done .But I want to know what these metal lines are connected to in a metal fill Are they grounded(this way there will be not parasitic C) or left floating?
  17. D

    which metal layer is fastest?

    which metal layer should be used for reducing the over all delay.Lowest(M1 ) or highest(M6 )?
  18. D

    which metal should be used?

    Please answer this question as I am preparing for an interview There are 2 inverters connected in series.Justify which metal layer(lower like M1 or M2) or higher(M5 or M6) would you use to connect them
  19. D

    what is porosity of a layout? why is it important?

    porosity what is porosity of a layout? why is porosity of a layout important?

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