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    eDRAM bist - request for resources

    eDRAM bist I need any information about eDRAM classification and BIST
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    How to divide 100Mhz input clock to 10Mhz just by using D flip flop?

    Re: D flip flop Using 5 FFs will result clk/32. It seems that without combinational logic it is impossible to divide clk by 10. To minimize combinational logic a 3-bit LFSR can be used. Also an extra TFF with enable is required.
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    Pls help to find Data Sheet of Programable Encoder SCL1527

    programable encoder I need information about Programmable Encoder IC SCL1527. But information is placed only on Chinese sites. If there is some datasheet even in Chinese please point the link.
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    What is the dufference between CF775 and PIC16C75

    pic16c75 cf775 Thank you very much for your help.
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    What is the dufference between CF775 and PIC16C75

    cf775 I have some links pointing that CF775 is the same as PIC16C57. Is this true? Please help.
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    How to use march test algorithms ?

    Re: march test There is a lot of informationabout about memory testing and especially about MARCH tests in Internet. At first you need to familiarize yourself with that background. After, if there still questions, I'm ready to answer on them
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    What is the meaning of at-speed testing?

    Re: At-speed testing Do you want to test memory or something else ? If memory, then BIST is the cheapest and more reliable solution
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    What are the effects of GALS on chip design?

    Re: GALS To begin acquaint myself with GALS - general description will be more useful Thanks
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    What are the effects of GALS on chip design?

    Re: GALS Guys, Is there any papers or books describing GALS more detailed?
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    how to Write verilog for selecting part of bus

    I believe that the optimal way is always@(length or A) begin case(length) 0 : B[0:15] = A[0:15]; 1 : B[0:15] = A[1:15]; 2 : B[0:15] = A[2:15]; ... 15 : B[0:15] = A[15:30]; endcase end
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    Statement unreachable (Branch condition impossible to meet)

    Re: Statement unreachable (Branch condition impossible to me The fact that wr is declared as reg doesn’t mean that wr is FF. In your verilog code the behaviour of wr is net (wire). So the code wr <= ~wr generates combinational loop, which is unacceptable in poor digital design.
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    How to model #delays in RTL?

    Re: #delays in RTL #delays are necessary in RTL when in projects are behavioral models of non-digital circuits, for instance memory. In memory behavioral models are setup, hold, recovery and other timing checks. The only way to provide this timing requirements is use #delay. Another advantage...
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    Pic or 8051 , which is perfect for me?

    I believe that it does not worth to change 8051 family. There are many 8051 microcontrollers equiped with different peripherials. You should just see MCU of another company.
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    Pic or 8051 , which is perfect for me?

    I believe that it does not worth to change 8051 family. There are many 8051 microcontrollers equiped with different peripherials. You should just see MCU of another company.
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    what is the typical read/write time of ram in ASIC and FPGA?

    Re: what is the typical read/write time of ram in ASIC and F Read and write timings of embeded SRAM depends on the following parameters - is it High Density or High Speed ? many parameters. - technology - 18um,13um,90nm,65nm - quantity of bits in required memory For high speed memories clock...
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    Is dualport ram much more costly than singleport ram asic?

    Re: Is dualport ram much more costly than singleport ram asi Viragelogic is the another SRAM IP provider ( www.viragelogic.com ) They also provide embeded BIST/BIRA solution. I don't thik that the prices of SP and DP are that different.
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    which is better AVR or PIC microcontrollers

    All necessary information is available at www.atmel.com. Also there are many usable AppNotes.
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    which is better AVR or PIC microcontrollers

    Definitely AVR. I have experience with AVR, and familiar with PIC. AVR's instruction set, peripherals and memory map are very well organized. Quality shareware also available.
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    VCS, NC-Verilog and Modelsim, which is the best simulator??

    Re: VCS, NC-Verilog and Modelsim, which is the best simulato ModelSim is convenient to use during project's debug. VCS is better during RTL and gate level verification especially for big projects.

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