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Q1. To achieve highe gain in voltage amplifer output resistance is increased.
And increasing output resistance may seem to make the speed of circuit quite
susceptible to the load capacitance. why???
Q2. Total bias current in folded cascode case is required higher than...
When I simulated VCO(in this case ring) using netlist extracted from layout design
, I got to see no oscillation at the out for some of the voltages. say, vco simulated
for 1- 1.8 volt. From 1-1.6 V , no probs, but at 1.7 & 1.8 volt simulation fails. Oscillator doesnot oscillate.