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    Synthesizing a large memory using Genus 19.1

    I have a problem synthesizing my design. Its submodules can be synthesized however when I want to synthesize the top module, Genus doesn't finish the elaboration. But there are no errors, because I check it with Modelsim to see if there is any. Also by reading the HDL file in Genus I don't...
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    tangent hyperbolic hdl design for ANN activation function

    Hi, I need to implement an hdl of hyperbolic tangent for Artificial Neural Network activation function. I've searched a lot but unfortunately I wasn't able to find a proper version as most people have used IPcores to implement it. Could anyone help me with it?
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    ISCAS 89-s38417 testbench required

    Hi, I need to generate a saif file for iscas 89 s38417 benchmark. I need a good testbench for that. I searched the previous posts and I found a link for that but it doesn't work anymore. could anyone help me with that.
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    Extracting MOSRA LEVEL 3 Parameters and values

    Do anyone know how can I extract MOSRA Level 3 parameters for a specific library file when I'm using hspice? I wanna measure the aging for standard cells of that library. Also do these parameters will change based on temperature? I've found a video about that in synopsys website but it doesn't...
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    Connecting FPGA to computer using ft232rl module

    Hello, I'm trying to send and receive data to/from fpga using ft232rl module(rs232). I'm using mojo v3(spartan 6 lx9). however I have tried to produce baud rate and receiver module, I'm not able to receive data from ft232rl. my baud generator is like this: module baud( clk, rxclk_en ); input...
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    instantiate a distributed ram using core generator in xilinx ISE

    hello. I try to implement a distributed RAM using ISE IP core generator but I have this warning: WARNING:HDLCompiler:1499 - "E:\M.Sc\ISE projects\ipcore-test\test2\ipcore_dir\myram.v" Line 39: Empty module <myram> remains a black box. my verilog code is : module test2( data_in, clock...
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    word's length of single port RAM

    hello. I have a verilog code for r single port ram : Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 module RAM ( clk, we, en, addr, din, dout ); input clk; input we; input en; input [5:0] addr...
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    using modelsim with tsmc 0.18u library

    hello can anyone give me a hand about using modelsim with tsmc 0.18u library? I wanna use modelsim as my verilog code simulator and I wanna have timing analysis of my code in modelsim with tsmc 0.18u. if it is possible can anyone tell me how? and send me the essential files.
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    how to fix WARNING:Xst:1710

    hello I'm trying to simulate a simple ROM(read only memory) in ISE 14.7 but unfortunately I have a warning during synthesize xst. WARNING:Xst:1710 - FF/Latch <data_out1_5> (without init value) has a constant value of 0 in block <ROM>. This FF/Latch will be trimmed during the optimization...
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    [SOLVED] xilinx timing analyze using modelsim SE

    Hello I'm trying to simulate a simple D Flip Flop in xilinx 14.7.I've wrote the testbench and I set the modelsim as simulator an I did the behavioral simulation without any problem but when I try to simulate the place & route simulation I can't see the result. This is my code : module dff(in...
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    verilog implementation of a viterbi decoder

    hello everybody. I'm trying to implement a viterbi decoder. I actually know the algorithm but I need to know the implementation techniques. could anybody introduce me an appropriate article or book. I want to know the concepts of traceback,register exchange and PNPH (Permuation Network based...

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