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    Verification methodology of motion estimation in H.264/AVC

    Hi; I am currently doing Motion estimation (ME) in H.264/AVC. My question is about verification methodology of motion estimation in H.264/AVC. Who has some experiences in this please help me? Could anyone interested in discuss together? Any suggestion is welcome. Many thanks Win3Y
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    Making signal delay and hardwire cost issue? Thank you

    Hi everybody; I wanna make some control signals delayed 10 or more than 10 clock cycle. I just know the way like this: reg [Nbit - 1:0] control_1_delay,control_2_delay,control_3_delay...control_10_delay; always@(posedge CLK ore negedge nRESET) if (!nRESET) begin...
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    How to design a comparator N-bit with lowest cost?

    Hi everybody; Is there any way to design a comparator N-bit with lowest cost? The comparator I made as following: input [N - 1:0] INP0, INP1; output [N - 1:0] MIN; assign MIN = (INP0 < INP1)? INP0:INP1; I wish to make another comparator that occupies smaller hardware cost. Thanks. W3Y.
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    Need a solution like multi-port SRAM, thank you!

    Hi everybody; I need the solution for this problem: Originally, I used 3 block RAMs (same content) with 3 separate Address reading signals. For saving reason, I just have only one block RAM, so what the solution for this problem in case budget cycle is limited (timing constrained). If it is...
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    Is there any problem in a design with a lot of wires?

    Hi Everybody; I am going to fabricate my design using DC, Prime Time and Astro. But I am wondering there is any problem in the design with a lot of wires while implementing Back-End work? Is there anyone had experience with this? My design has 3 modules connected each other by some wires...
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    Is data hazard in pipeline occurred or not in this case?

    Hi Dears; Pipeline has 3 stage such as: Memory Read(MemR)(@slot0), ST1(@slot 1), Memory Write (MemW)(@slot2). At slot2: (MemW) Memory write back to register buffer A. But at the same time, at slot2: (MemR) memory read data from the same register buffer A. My doubt is that whether data hazard in...
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    POWER consumption on BLOCK RAM?

    I found the answer for it ^ ^. W3Y
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    POWER ESTIMATION design - I found

    POWER ESTIMATION design I found
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    The technology library contains power information ?

    Dear Friends; The library that contains and supports power information is important for power estimation, isn't it ? Could somebody tell me about this kind of technology library and how to add in my testbench ? Thank you very much. W3Y
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    Comparison between results of Prime Power & Power Compil

    Hi All; I am trying to make the comparison of power consumption between my architecture and previous design. Other authors used Prime Power to measure their design but I just have Power Compiler. My question is that Can my design compare with their design without having the same Power...
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    Optimization Power consumption using Design Compiler

    power compiler rtl2saif Hi All; I am trying to optimize my design using Power Compiler (Synopsys) and looking for Power Compiler' Usermanual and Tutorials. It seems to be not available in this forum and Synopsys site as well. Could anyone give me some advices? Many thanks in advance. W3Y
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    Ask about parameters in Flow Summary Section(see picture)

    Hi Everybody! The below figure is Flow Summary Section and Timing Analysis Result (by Quartus). Please tell me know the signification of these below parameter: Total combination function - registers - pins - ALUTs I need to know the relation between them and "Gate count"? How about "Max...
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    How to obtain pixel data from file hex form for simulation?

    For simulation, by using verilog how can I code the programme to obtain pixel data from file hex form. Plesea show me the books, syntax, etc... Thank you very much!
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    Module for calculation SAD motion estimation using 2D-Tree

    Hi! I am coding the module that calculate SAD between current and reference block using 2D-Tree Architecture. It includes 2 module: module calculation+module control (I think so) About module calculation SAD, I formed it as following: + Input includes 32bit for 4pixel current and reference. +...
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    Need some hints about getting pixel data from memory on FPGA

    Hi, everybody! I do not know how to code a module that have function to get pixel data such as current pixel and reference pixel from memomy for calculation motion estimation. Pls give me some advice to implement it. For example, the output of above module is pixel data that synchronize by clock...
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    Need some advices about implement H.264 on FPGA (small part)

    I am going on implementation H.264 on FPGA namely as "calculate SAD by using 2-D tree architecture and implement it on FPGA (on platform FPGA such as HBE)". I think that it include 3 parts as below: - Input modulle is to get and process pixel on RAM - Calculate modulle is to calculate SADmin -...

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