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    US Silicon Valley San Jose: Sr. Application Engineer 2

    same public company as last post, please contact me as soon as possible if you are interested. Desired Skills & Experience • Minimum of five years plus of experience in CMOS camera applications, including hands-on experience with CMOS imagers in application test and design and helping...
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    US Silicon Valley San Jose: Sr. Application Engineer-USB

    Nasdaq 500 company, with stock option, bonus, 401k matching, relocation, etc If you are interested, please contact me as soon as possible. Desired Skills & Experience C, C++ and USB and Firmware 5+ years of experience on firmware and system design. USB, Camera, and Image sensor knowledge is...
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    simple interview question (1) on PLL and answer, but...

    Q: A PLL as a center frequency of 10^5 rad/s, Ko=10^3 rad/s/v, Kd=1V/rad. Assume there is no other gain in the loop. Ask: 1. Determine the loop bandwidth in the first-order loop configuration. 2. Determine the single-pole, loop-filter pole location to give the closed-loop poles located on 45...
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    A class-AB output from Huijsing's opamp theory and design

    op amp theory on page 155, figure 5.3.18 in Huijsing's opamp theory and design, He said, for this general-amplification feedforward biased class-AB output stage, 1. "Q3, Q5, Q4, Q6 form a positive coupling loop with a current gain of slightly lower than1, which keeps this loop stable." I...
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    Opamp offset in BandGap Reference

    bandgap offset Hi there, I am wondering whether anyone can guide me for the following questions. Appreciate your help. 1. The first one is a naive question, I forgot why CMOS diff-pair opamp always has very larger DC offset, comparing with bipolar-diff-pair opamp? 2. Why opamp offset is one...
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    VHDL coding questions about using process and if statements

    VHDL coding question Hi all, I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl...
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    one more interview question

    the question is "Typically, what breaks first on a MOSFET as voltage bias is increased, the gate or the drain diffusion?" I anwsered "gate will be broken first due to the thin oxide layer". But I could not explained why not drain diffusion at that moment? Any help on this? Appreciate
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    another interview question

    Dear all, the question is "What accuracy do you expect from a typical untrimmed bandgap? " I answered "The accuracy of untrimmed bandgap depends on the accuracy of the on-chip resistor; I don’t know the exact quantity about this." This is also incompleted. Need help. thanks.
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    interview question needed to help out

    Dear all, The question is "What is the physical meaning of gm when MOSFET operating in saturation?" I answered "Transcoductance gm reflects the change in the drain current divided by the change in the gate-source voltage. It represents the sensitivity of the device." But it seems not...
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    Nonlinearity question

    Dear all, recently, I got a phone interview question regarding "what is nonlinearity" and "which technique to reduce nonlinearity in Analog or Mixed-signal or RF IC design"? (I am fresh graduate) I anwsered the techniques to reduce nonliearity; 1.source degeneration 2. feedback. But this is...
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    QuartusII compiler warning for FSM controller

    Hi there, I got a bunch of warnings when i compile my controller, a finite state machine written in VHDL. Here are the warnings I got: Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "partition1" may not be assigned a new value in every possible path through...
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    Urgent: about a compilation problem in QuartursII 5.0

    design does not contain any logic Dear Everybody, I have a quick question about the compiation problem in Quarturs II 5.0. After I create a testbench to test LFSR, I always get the errors said: "Error: Can't synthesize current design -- design does not contain any logic ......" But...
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    how to load Simulink mdl file

    matlab mdl Dear everybody, I searched from website and downloaded some *.mdl files (basically, text format). But I found I couldn't just open them directly from Simulink-> new modle window (untitiled), since the lots of blocks will be displayed as errors and lots of warnings in Matlab main...
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    current-controlled current source in Spectre

    current controlled current source Dear everybody, I am wondering how I can use "cccs" from analoglib in Cadence to build an ideal differential current amplifier. The cccs is two-port instance, no like vccs and vcvs, which are 4-port instances. Which properties should I specify besides the...
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    which book is best for Verilog-AMS and VHDL-AMS

    verilog ams prentice hall Hi there, I am wondering which books are best for own for either Verilog-AMS or VHDL-AMS. is this a best one for VHDL-AMS? The System Designer's Guide to VHDL-AMS (The Morgan Kaufmann Series in Systems on Silicon) (Paperback) by Peter J. Ashenden, Gregory D...
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    Matlab and simple multiplexing function?

    Dear all, I got a very quick question that I don't know whether I can use Matlab to implement a very simple multiplexing function in digital logic circuit. More specific, say, there is one clock signal and one two-bit control signal. In digital logic circuit, then I can use this two-bit...
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    which is correct configuration?

    Hi there, It seems no so many people interested in So, let's put it in a simple way. In the below figure, which is appropriate structure to test step response for slew rate measurement in Cadence spectre? Note: the opamp is single stage to drive capacitive load. Which is correct? or All...
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    a simple question for OTA step response configuration

    output stage current ota hello everybody, I got a question for the step response configuration, which I have not thought about clearly. My opamp is single stage fully differential fold-cascode OTA to drive capactive load. The CMFB is switch capacitor circuit. When I tried to test step...
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    A question for Slew Rate Function in Cadence Calculator

    slew rate calculation Hello everybody, When I tried to use "slewRate" function in waveform calculator of Cadence Analog Design Environment , I found I could get two different SR values for the same ramp of the same curve by using two options seperately, which are either "initial value Y at...
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    A case study:OTA with SC_CMFB and PAC simulation

    Hello Everybody, I attach a figure below which shows fully-differential fold-cascode one stage opamp with SC-CMFB. Then in my next post, there is another figure, which I think it can be used as CMFB structure with equavilent resistors (which I call R-CMFB here). This CMFB structure is variant...

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