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  1. H

    Analog PLL or Digital PLL

    Hello, many advantages are mentioned in the papers related to Digital PLL but I see also many designs that still use Analog PLL. Can anybody help me to know that why still analog PLLs are popular and what are their advantages? Thanks
  2. H

    [Moved]: Bode plot of pll in time domain

    Hello, How is possible to do stability analysis for the time domain pll in simulink? is it possibe to use bode plots from simulink linear analysis for time domain pll?
  3. H

    [Moved]: Phase noise modeling of the digital controlled oscillator

    Hello, I have a basic question about the noise simulation for the digital controlled oscillator in matlab. There is two profiles for the phase noise as the attached figures. One (left side) is obtained by importing the phase noise at different offsets to matlab. The other (right side) is...
  4. H

    Frequency of a random pulse over time in simulink

    Hello, i want to plot the frequency of a random pulse over time. Does anybody knnow haw cann I do this in simulink?
  5. H

    Transfer the phase noise characteristics from matlab to simulink

    Hello, i have the phase noise characteristics of vco in matlab. I want to transfer this to simulink for further processing. Does anybody have an idea that how it can be done? Thanks
  6. H

    Simulating PLL phase noise in simulink

    Hello, does anybody know how to add phase noise to the VCO in the PLL to simulate the PLL phase noise in simulink? Thanks
  7. H

    Digital phase locked loop adder

    Hello I should implement a proportional- integrator loop filter. in the integral part, there is one accumulator which I implement using full adder as in the picture. there is 6 bits at the inputs of full adder and the output with carry is 7 bit. But it seems that here the carry is ignored, does...
  8. H

    Frequency control word to a digital phase locked loop

    Frequency command word to a digital phase locked loop Hello, does anybody know that what is the frequency command word for the implementation of the DPLL? I mean what kind of input source should I give to it?
  9. H

    [Moved]: Digital phase locked loop

    Hello, I want to learn about digital phase locked loop design. As far as I search, there are implementation about it in some thesis or articles which explain their main blocks like TDC, DCO,... I understannd their concepts but I have problem about the interface to connect this blocks. for...
  10. H

    VCO frequency and area

    Hello, I have a basic question about LC-oscillators. I will consider a case that the sampling clock of 1GHz is needed. Since the inductors get large area on chip, what is the trade offs that I use a 8GHz VCO and divide it by 8 instead of using a 1GHz VCO? Thanks
  11. H

    resolution of time to digital converter

    Hi, in the papers when they talk about the ring oscillator based TDC, they mention the resolution as 1/fosc but I think that it should be 1/2Nfosc where N is the number of stages in the ring structure. Please let me know if someone has experience?
  12. H

    [Moved]: find the maximum value of a signal during a period

    Hi everbody, I want to find the maximum value of a periodic signal during a period and then reset at the end of period and repeat the previous step. I need this in simulink but I have problems. Does anybody know about this??
  13. H

    convert the output of counter to an integer in simulink

    Hi, I have the output of counter that is increasing in a stepwise. I nneed to have the maximum number to conver it to binary. Does any body have experience? for example in the attached fig, the counting number at the output is 3 and I want to extract it.
  14. H

    [Moved]: Time to digital converter design for DPLL

    Hi, I am new to digital PLL design. unfortunately I could not find and references that show the output of TDC during lockinng process of DPLL. If someone knows any reference to show the output of TDC in lock state of DPLL, please let me know.
  15. H

    [Moved]: Phase locked loop jitter at 1GHz

    Hello, there are many papers about high frequency PLL>10GHZ in the technology below 90nm with LC VCO that their rms jitter is in the range of less than 500fs. I need to know the rms jitter at 1GHZ frequency to compare my design requirements. I could not find good references for them but I gussed...
  16. H

    [Moved]: pseudo thermometer to binary decoder

    Hi, I need a structure that convert the number of 1s at the output of TDC to binary bits. Is there any model using digital logics or matlab code ??
  17. H

    counter implementation in simulink

    I have a counter design in simulink that is active with rising edge of the clock. I use enable port to activate the output when the pulse level is high and reset the counter to initial state. But in my design when the pulse level is low, counter keeps the previous state. Does anybody have an...
  18. H

    Time to digital converter design

    Hi, I am searching for a complete design of a ring oscillator based TDC. Can anybody suggest me a referennce with the detailed design implementation?
  19. H

    varactor using thick oxide transistors versus thin oxide one

    Hello, I simulated a thick oxide pmos varactor which the gate is connected to 500mv. For the C-V curve, the tick oxide has a linear characteristic. But for a thin oxide varactor, the capacitance value till vsg<0, is constant. does anybody know that why for the thick oxide one the capacitance is...
  20. H

    VCO phase noise problems

    Hi, I have the measurement results for an LC-VCO which is working at 2GHz and the design is based on conventional structures. The measured phase noise is -90dBc/Hz but the simulated phase noise using RC extracted design is -110dBc/Hz. Does anybody have experience that why the phase noise is much...

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