Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. J

    Resuming simulation from CLI mode in VCS

    Dear Friends, I am running VCS to dump fsdb files. The number of fsdb files are large in number, which are bit difficult to handle them at a time because each of the file require some GB of spaces. So, its really impossible to dump all the files at a time. I thought of handling this problem...
  2. J

    Need a guideline for using tetramax

    Hi Friends, Here I am attaching one script fille for Tmax flow for generating test patterns. The # and // lines are comment lines. For genrating test patterns Tmax need few input files: 1) source netlist file 2) class.v file for library (note u can have any other library also)...
  3. J

    Fault simulation using Tetramax..External patterns help! Plz

    Hi Rohit, What u have to do is; 1) first you save the internal patterns in .wgl format (I think u r looking for this format). This you have to do during the pattern generation time. Command: cmd1) set patterns internal cmd2) run atpg...
  4. J

    Scan Chain Test Pattern of ATPG tool

    The scan chain patterns are needed to be shifted in during scan initializatio operation. So if the patterns are of 0->0 or 1->1 form then there will be no toggling during the shift operation, where as if the patterns are of 01010 then there will be maximum toggling. These toggling are not good...
  5. J

    generating test vectors uing atalanta

    I think following will work. atalanta-M -c n -t c432.pat -W 1 c432.bench Or u can try various combination of -c n option with -t and -W option. Check the web: http://service.felk.cvut.cz/vlsi/prj/Atalanta-M/ REgards, JayNarayan
  6. J

    Which Eda tool verify functionality and does the timing analysis of MultiCore design?

    MultiCore design Have you tried with VCS for functionality checking and Prime Time for timing analysis. These are Synopsys tools. With regards, JayNarayan
  7. J

    i need a matlab code for Person-by-Person Optimization

    Dear all One request, please give a nice title to your post instead of just "Dear all"
  8. J

    text File reading and writing in VHDL

    I have just started learning the VHDL. I found one logical error in the following while loop. Error : The while loop also contain the exit statement which will stop your program evreytime it does the file reading, because the exit statement will be true after the reading the last line in...
  9. J

    Extra pattern on top of the existing pattern set

    Hi friends, I have one small query. I hope you might be wel aware that to increase the fault coverage, in some cases it is required to add some extra patterns on the top of the currently available patterns. I wanted to know, when these patterns are available during the scan desing cycle...
  10. J

    Scan optimization: is it during scan insertion or ....

    Hi frnd I have one more small question. The test pattern (transition fault) generated using the gate level netlist obtained just after scan synthesis and the pattern generated using the netlist obtained after astro will be same or they differ. I have not done any experiment yet. Any...
  11. J

    scan reordering and scan stitching

    Hello frnds, Do any one have idea about the clock rate at which the shift operation is performed in scan testing. I need proper references. If you have kindly give me the title of paper. PreThanks, JaY
  12. J

    scan reordering and scan stitching

    Thanks Raphy for your reply. I too understood the same as you explained. Thanks, Jay
  13. J

    scan reordering and scan stitching

    Hi frnds, This post is regarding the difference between the scan reordering and scan stitching. I came across the book "The VLSI test principle..." by Xioqing Wen et al. where they have defined the Scan stitching methodology as the final connection between the scan cells, the out put of...
  14. J

    Scan optimization: is it during scan insertion or ....

    Hi frnd, The discussion got interesting shape. I thank all of you for interesting discussion. I am just curious about the question asked by raju to chyu. I will be following the discussion. Regards, JaY
  15. J

    Scan optimization: is it during scan insertion or ....

    hi vcd, thanks for responding me. I am still not convinced about the scan optimization done by DFT-compiler. During the compilation time or during dft insertion there is no information about the placement and routing, I mean there is no way to extract the geometrical information during scan...
  16. J

    Regarding design for testability

    Hi friend, I want to know, whether the scan chain order will remain same for the synthesized netlist even after the P & R. I doubt becoz placement n routing tries to optimize the routing-related delay which may break the initial order of scan cells. Actually the problem is, I have done...
  17. J

    calculate min clock period under different assumptions

    Hi, thanks for posting nice puzzles. Here is my attempt. 1) TW = (12 + 22) * 2 = 68 based on 50% criteria I have not added set up time, bcoz inverter delay is > set up time 2) 12 + 22 = 34ns clock should remain in negative level. and 14 ns it should be in positive level. putting...
  18. J

    Scan optimization: is it during scan insertion or ....

    Hi DFTian, I am bit doubtful about the scan optimization ( constraint: power, area), exactly when it is done, is it during scan insertion that is done with DFTCompiler or it has to do with Astro (synopsys tool for scan optimization and ....). Please give your healthy reply...
  19. J

    DFT Query - request for resources

    DFT Query Read Following Book/Manual: 1) Essential of Electronics Testing By. Prof. V. D Agrawal 2) TetraMax Manual " Available in Net " 3) Also You can look at the Synopsys Web site ..... Cary on ...... Regards, Jaynarayan
  20. J

    career in digital vlsi field ?

    Intel is the best option for you foster in VLSI design. Also other option could be to do some research work with some professor either in some IIT or IISc. In IIT madras there is very good professor Kamokoti working in the VLSI field, you can write him mail to work with himm may as a research...

Part and Inventory Search

Top