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  1. M

    how to calculate cache size

    how to calculate cache size?
  2. M

    what is a zero phase filter

    what is a zero phase filter how to design it in matlab?
  3. M

    filter transfer function (s+w)/s ?

    what does this transfer function (s+w)/s mean for a filter?
  4. M

    how to design an 8-bit sigma delta ADC

    forget about that, it is just a D/A
  5. M

    how to design an 8-bit sigma delta ADC

    From the figure, x(n) is the 1-bit stream. After the digital filter and decimator, what will be y(n) be?
  6. M

    how to design an 8-bit sigma delta ADC

    At the output we get 1-bit data stream, how can it be 8-bit? thx
  7. M

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received

    Not the same time. It should be clock 1, 2, 3, and clock 4 control FIFO
  8. M

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received

    I know how to do with one input port to one output port. But how about two input ports? I need a mux to choose from the two ports. What would be the achitecture look like? It is one input above
  9. M

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received

    Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received at port1 or port2 and deliver them in the same order at port3. Assume that each data word is 8-bit wide. The external systems that provide data at port1 and port2 use the sender originated protocol and the...
  10. M

    • Give me an example of asynchronous finite state machine

    • Give me an example of asynchronous finite state machine
  11. M

    List all possible ways to minimize the power dissipation of an ASIC chip

    List all possible ways to minimize the power dissipation of an ASIC chip Thx
  12. M

    verilog code for intel 8085 processor

    who can give a verilog code for intel 8085 processor?
  13. M

    design a 8 bit processor with the following specifications

    I think you are right, but there is another problem: 10 010 s2s1s0 : SUB r (subtract reg s2s1s0 from reg A) 10 010 110 : SUB M (subtract memory contents from register A) For 010 is C as you said, the two operation above should be add s2s1s0 or M to C, how can it be a subtraction? And what are...
  14. M

    design a 8 bit processor with the following specifications

    I do not know what the opcodes means. for example, 111 stands for A, but there is no 111 in the code, how can it relate to A? 01 d2d1d0 s2s1s0 : MOV r1, r2 (copy reg s2s1s0 to register d2d1d0) 01 110 s2s1s0 : MOV M, r (copy reg s2s1s0 to memory) 01 d2d1d0 110 : MOV r, M (copy memory contents...
  15. M

    design a 8 bit processor with the following specifications

    Design a 8 bit processor with the following specifications1: 1. The processor has seven 8-bit registers A, B, C, D, E, H and L. 2. It connects with an external memory containing 32 8-bit words. The memory has a tristate output with active low signals rd and wr. 3. It has instructions MOV, LDA...
  16. M

    why no clock and reset signal

    I got all the signal, but it does not work correctly,,,I don't know what's wrong
  17. M

    why no clock and reset signal

    Here is the whole thing: 1.Problem: Design a system that accepts an input data stream x0, x1, x2, . . . at Port1 and produces a stream of output data points at Port2. Four output points are computed for each set of four input points. The output stream should look like: x2, x1 + x2, x0 − x1, x3...
  18. M

    why no clock and reset signal

    I am designing a system that accepts an input data stream x0, x1, x2, . . . at Port1 and produces a stream of output data points at Port2. Four output points are computed for each set of four input points. The output stream should look like: x2, x1 + x2, x0 − x1, x3; x6, x5 + x6, x4 − x5, x7; ...
  19. M

    why no clock and reset signal

    `timescale 1ns/1ns module test_project1; reg clk,reset; reg [7:0] port1; wire [8:0] port2; integer file; initial file=$fopen("proj.dat","rb"); always@(posedge clk) $fscanf(file,"%d",port1); initial begin clk = 0; reset = 0; reset = #1 1'd1; reset = #2 1'd0...
  20. M

    syntax error, unexpected wire, expecting";"

    Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong? code: module test_project1 wire clk,reset; reg [7:0] port1; wire [8:0] port2; reg eof; integer project1; initial project1=$fopen("proj.dat","rb"); always@(posedge clk) begin eof=feof(project1)...

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