Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. E

    Where to download liberty parser from Synopsys?

    I used to download the source code from https://www.opensourceliberty.org, but I couldn't find the link here now. Does Synopsys completely give up this tool?
  2. E

    Is there a static RTL coverage analyze tool?

    Hi, guru: I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation? For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle" I...
  3. E

    How to measure reference clock to q delay in hold sweep?

    Hi, I try to sweep hold time (latency between data and clock edges for a flop) and measure the impact on clock -> output q delay vclk clk 0 pwl (0ps 0v 20.0ns 0v '20.0ns+clk_slew' vdd_sup '30.0ns+clk_slew' vdd_sup '30.0ns+2*clk_slew' 0v '40.0ns+2*clk_slew' 0v '40.0ns+3*clk_slew' vdd_sup) vd...
  4. E

    Anyone is using Liberty Parser?

    This is not I was talking about, but thanks anyway.
  5. E

    Anyone is using Liberty Parser?

    I am using Liberty Parser 2.5 from Synopsys to parse and process liberty files. There is a Perl interface in the package so I use it to make my programming easy. However, I found one issue in in this Perl interface: it's good to read .lib but when it comes to write out a modified liberty to a...
  6. E

    Convert verilog gate netlist to hspice transistor netlist?

    transistor netlist We tried nettran or icfb to convert a verilog gate-level netlist to spice transistor level netlist. However, we found these tools need the transistor information for standard cells to perform a complete translation. Otherwise, they simply do the syntax converting. Can anyone...
  7. E

    How to use SolvNet properly

    I just register a SolvNet account using my company's email and siteID. It seems that there are many softwares downloadable and many documents/trainings too. Anyone can tell me what's the proper (legal) way to take advantage of these resources? Thanks a lot!
  8. E

    How to dump spice netlist in Astro?

    spf netlist Someone on this forum said this can be done in Calibre but I don't have it. I found that the parasitic R, Cs can be export in Astro, but not the design itself. Maybe I missed something in Astro or I have to do it with some other tools? Thanks for help!
  9. E

    Understanding synthesis library

    Anyone can help me out? I need a way to read out the infomation in the synthesis library (.db) Thanks!
  10. E

    Understanding synthesis library

    Anyone knows how to read out the information in the synthesis library for desgin compiler? It is not in the text format. Thanks!
  11. E

    How much is the switching activity factor?

    What's the resonable assumption of switching activity factor "alpha" or it's very application specific? Note: Pdyn = alpha * CL * Vdd^2 * f for dynamic power consumption Thanks a lot!
  12. E

    How does Vth scale down with technology nodes

    I think the Vth should go down when scaling down to deeper sub-micron technology nodes for shorter channels and etc. but Predictive Technology Model (PTM) assumes in the contrary direction **broken link removed** from 130nm to 22nm BSIM4 models, the vth0 parameter in model cards goes from...
  13. E

    How to calculate the depth of FIFO?

    I think 32(or 33) is correct. The worst case is then two writes (80words for each) are continuous in two 100-clock slots 1------20-----------------100 101------------------181--------200    WWWWWWWWWW WWWWWWWWWW    RRRRRRRRRRRRRRR RRRRRRRRRRRRRRR This scenario will left 32words unread.
  14. E

    fsm sequence detector

    overlapping sequence detector notes There is another kind of questions: how to detect a pattern in the last several input samples: 1) Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples. For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0...
  15. E

    A basic question on Verilog simulation

    In IEEE standard 1364, it says the following code module test; wire p; reg q; assign p = q; initial begin q = 1; #1 q = 0; $display("At time: %t, the value is %f\n", $realtime, p); end endmodule could either display p as a "1" or "0". I can't understand why. #1 q = 0...
  16. E

    A verilog VPI problem

    Hi, everyone: I have a verilog code : module test; reg a, b, ci, clk; wire sum, co; addbit i1 (a, b, ci, sum, co); initial begin $set_delays(i1.a, 2.3, 2.4, 2.5); #1 $finish; end endmodule module addbit (a, b, ci, sum, co); input a, b, ci; output sum, co...
  17. E

    Leading ASIC design companies in USA

    Can anyone provide a list of such companies? thanks a lot
  18. E

    A Verilog VPI problem

    xxtern I am using ncverilog (LDV4) to run a simulation with VPI functions (loadvpi option) but get the following errrors: ncsim: relocation error: ./libvpi.so: undefined symbol: vpi_get_userdata I checked vpi_get_userdata prototype in vpi_user.h: XXTERN void *vpi_get_userdata...
  19. E

    A problem on PLI for Verilog

    specify gate delays in testbench in verilog I run a testbench and found that the gate delays are not impacted. Did I use acc_replace_delays() in the wrong way or it's not implemented in ldv4? It's quite wierd to me because I was following the examples in cdsdoc of ldv4. Can anyone help me...
  20. E

    A problem on PLI for Verilog

    new_rise The new delays are printed based on the values I feteched from the simulator. acc_replace_delays(gate, new_rise, new_fall); acc_fetch_delays(gate, &new_rise, &new_fall); io_printf("Gate %s new delay: rise-%f, fall-%f\n", acc_fetch_fullname(gate), new_rise,new_fall); Is...

Part and Inventory Search