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I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation?
For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle"
I try to sweep hold time (latency between data and clock edges for a flop) and measure the impact on clock -> output q delay
vclk clk 0 pwl (0ps 0v 20.0ns 0v '20.0ns+clk_slew' vdd_sup '30.0ns+clk_slew' vdd_sup '30.0ns+2*clk_slew' 0v '40.0ns+2*clk_slew' 0v '40.0ns+3*clk_slew' vdd_sup)
I am using Liberty Parser 2.5 from Synopsys to parse and process liberty files.
There is a Perl interface in the package so I use it to make my programming easy.
However, I found one issue in in this Perl interface: it's good to read .lib but when it comes to write out a modified liberty to a...
We tried nettran or icfb to convert a verilog gate-level netlist to spice transistor level netlist. However, we found these tools need the transistor information for standard cells to perform a complete translation. Otherwise, they simply do the syntax converting.
I just register a SolvNet account using my company's email and siteID.
It seems that there are many softwares downloadable and many documents/trainings too.
Anyone can tell me what's the proper (legal) way to take advantage of these resources?
Thanks a lot!
Someone on this forum said this can be done in Calibre but I don't have it.
I found that the parasitic R, Cs can be export in Astro, but not the design itself.
Maybe I missed something in Astro or I have to do it with some other tools?
Thanks for help!
I think the Vth should go down when scaling down to deeper sub-micron technology nodes for shorter channels and etc.
but Predictive Technology Model (PTM) assumes in the contrary direction
**broken link removed**
from 130nm to 22nm BSIM4 models, the vth0 parameter in model cards goes from...
I think 32(or 33) is correct.
The worst case is then two writes (80words for each) are continuous in two 100-clock slots
This scenario will left 32words unread.
overlapping sequence detector notes
There is another kind of questions: how to detect a pattern in the last several input samples:
1) Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is
0 1 0 1 0 1 1 0...
In IEEE standard 1364, it says the following code
assign p = q;
q = 1;
#1 q = 0;
$display("At time: %t, the value is %f\n", $realtime, p);
could either display p as a "1" or "0". I can't understand why.
#1 q = 0...
I am using ncverilog (LDV4) to run a simulation with VPI functions (loadvpi option) but get the following errrors:
ncsim: relocation error: ./libvpi.so: undefined symbol: vpi_get_userdata
I checked vpi_get_userdata prototype in vpi_user.h:
XXTERN void *vpi_get_userdata...
specify gate delays in testbench in verilog
I run a testbench and found that the gate delays are not impacted.
Did I use acc_replace_delays() in the wrong way or it's not implemented in ldv4?
It's quite wierd to me because I was following the examples in cdsdoc of ldv4.
Can anyone help me...
The new delays are printed based on the values I feteched from the simulator.
acc_replace_delays(gate, new_rise, new_fall);
acc_fetch_delays(gate, &new_rise, &new_fall);
io_printf("Gate %s new delay: rise-%f, fall-%f\n", acc_fetch_fullname(gate), new_rise,new_fall);