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  1. roger

    How to define max_fanout max_transition max_capacitance ?

    max_transition Dear: How to define max_fanout/max_transition/max_capacitance in the design, please give me some advice or experience. B.R
  2. roger

    can any explain the hold time for me?

    I got the min path analysis here & I doubt the analysis Poin Incr path ---------------------------------------------------------------------------------- clock clk(rising edge)...
  3. roger

    how to avoid back slash "\" in dc

    as title how to avoid back slash "\" in dc tks
  4. roger

    What's the difference between dummy cell & spare cell?

    as title What's the difference between dummy cell & spare cell? tx
  5. roger

    Explain me the 4W on Lockup cells

    As title 4W on Lockup cells ? What ? When ? How? Where? TKS in advance
  6. roger

    synopsys design compiler workshop

    primetime workshop as title , anyone got the primetime workshop lab I wanna a copy to practice the instructions. TKS
  7. roger

    how to determine pin list

    Hi all: Is there any doc talkig about how to determine the pin list, Is there ant rule to follow? TX in advance
  8. roger

    How to reduce bus switching in the pad?

    Hi all: I am looking forward to some algorithms to reduce bus switching to reduce power consumption. pls give me some idea.
  9. roger

    What is SSTL & Why SSTL?

    What is SSTL & Why SSTL? tks
  10. roger

    how to set the appropriate constraints?

    Hi all: How to set the appropriate constraints? Is there any rule? about clk 1. set_clock_transition -rise -max a 2. set_input_transition -rise -min b about design rule 3. set_max_transition c 4. set_max_capacitance d how to decide a,b,c,d ? TKS in advance
  11. roger

    How to extract signal to start or stop dumping

    fsdbdumpon How to extract signals to start or stop dumping using VHDL, ModelSim? Please.
  12. roger

    Is ROM a "must" in up based design?

    Is ROM a "must" in up based design? cannot we replace ROM by RAM? what's the advantage of using ROM?
  13. roger

    Whats the difference between crystal and oscillator?

    crystal & oscillator crystal & oscillator , what's the difference? Pls give me some idea. :cry:
  14. roger

    SRL,ROR,... operator in VHDL

    vhdl srl when I use SRL,ROR,... operator in VHDL modelsim5.8sb shows # ** Error: ./rtl/SPI_Model.vhd(136): No feasible entries for infix op: "srl". # ** Error: ./rtl/SPI_Model.vhd(136): Type error resolving infix expression. # ** Error: ./rtl/SPI_Model.vhd(146): VHDL Compiler exiting # **...
  15. roger

    how to dump very long time simulation in modelsim VHDL?

    dumping signal in modelsim vhdl as title, If I dump as usual, the fsdb file will be huge, how to dump them by splitting time & different fsdb file.
  16. roger

    how to suppress warning in modelsim

    modelsim suppress warnings how to suppress the warning message in modelsim # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 1211550 ps Iteration: 1 Instance: /tb/tmp4/mot/mtc0/ad21 I tried to suppress them at...
  17. roger

    what about the IC-design job market in Silicon Vally

    ic design job market My companion would like to move to Silicon Vally, How about the current job opening , salary there?
  18. roger

    will JPEG2000 prevailing?

    will JPEG2000 prevailing? share me with your idea
  19. roger

    mpeg-4 or h.264 which will dominate the compression world

    mpeg-4 or h.264 which will dominate the compression world
  20. roger

    Who's goin to dominate the nex-generation HDL world?

    ghdl verilog systemverilog Verilog2001 System Verilog VHDL System C who's going to be the winner? share your idea with me 8)

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