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  1. C

    How to calculate inductance for non-RF use of on-die/on-pack

    Inductor Formula Hello Everyone, What Inductor formula should I use to calculate Inductance for non-RF applications on-die/on-package? Inductor I have to design should be able to take 4Amp and it's value should be arond 2uH. Will appreciate for an early reply... Regards, Chanchi
  2. C

    How to calculate inductance for non-RF use of on-die/on-pack

    Inductor Formula Hello Everyone, What Inductor formula should I use to calculate Inductance for non-RF applications on-die/on-package? Inductor I have to design should be able to take 4Amp and it's value should be arond 2uH. Will appreciate for an early reply... Regards, Chanchi
  3. C

    Very Low Jitter PLL Design

    Hello, I have been assigned a task to do a competitive study on very low jitter PLL's. The PLL has tight specs of 25ps peak-to-peak jitter in 0.13u digital CMOS process. 1)How feasible is it? If I use ring-oscillator based VCO, can I meet these specs? How much we can achieve by using a...
  4. C

    Large i/p Bandwidth Sigma-Delta ADC

    Thanks Btrend. I appreciate for your interest. I forgot to mention that both the TSMC process I mentioned are digital 0.13/0.18 process. Is the data you mentioned is feasible for Switch-Cap? With 16 bit linearity+High Bandwidth, what topology of OTA you will suggest? Regards, Chanchg
  5. C

    Large i/p Bandwidth Sigma-Delta ADC

    Hello Everyone, Is is possible to design a Sig-Del ADC(probably switch-cap based) with following specs? 1. I/P Signal Bandwidth = 2.2Mhz 2. Conversion Rate = 8Mhz 3. Linearity = 16 bit Process 0.13u TSMC or 0.18u TSMC. Regards, Chanchal
  6. C

    Test of DC/DC Converters

    Isn't the control loop affected by NO-Load situation? Like in Current Mode control, minimum ripple is needed for Loop Stabilization.. Chanchg
  7. C

    Test of DC/DC Converters

    Hello Everyone, Can anyone let me know how to test a DC/DC converter when NO load is present? Regards, Chanchg
  8. C

    Suggest me good references/books on designing Class D Amps

    Class D Amplifiers Hello Everyone, Can I suggest me good references/books on designing Class D Amplifiers? Regards, Chanchg
  9. C

    Standard table for resistors with tolerance from 0.1%-10%

    table of resistors Hello Everyone, I need to choose a precise a value of resistor from the datasheet of a vendor. That vendor has provided the resistor range with % tolerance. I need to choose an exact value but somehow the detail table is missing, especially for 2% tolerance. Can anyone...
  10. C

    Single Turn/Multi-Turn Potentiometers/Trimmers

    How different are Single Turn and Multi-Turn Potentiometer/Trimmers? Regards, Chanchg
  11. C

    Spice Models of Power Mosfet

    Can anyone help me out with Spice Models of a power mosfet? How can we test/characterisize a power mosfet using it's spice model? Regards, chanchg
  12. C

    DDR RAM performance based on Voltage Regulators

    Hello Everybody, Can anyone explain the affect of voltage regulators on the performance of DDR/DDR-II type of DRAM's? In other words, how the variation in power supply affects the performance of DRAM's? Regards,
  13. C

    Why Latched-Comparator are not preferred in PWM applications

    Hello Everybody, Why Latched-Comparator is not preferred in PWM block of a Switching Regulator? In other words, what is the advantage of OPAMP Comparator and Latch Comparator over each other? Regards,
  14. C

    Voltage Regulator Designs for DDR DRAMS

    Thanks to everyone... One more question... How the Regulator specs changes for DDR RAMS used in Desktops and those used in NOtebooks? Thanks,
  15. C

    What is SSTL_18 I/O Interface

    sstl_18 Can anyone enlighten me about SSTL_18 I/O Interface? Regards,
  16. C

    Voltage Regulator Designs for DDR DRAMS

    ddr ldo site:edaboard.com Hello Everybody, Where can I get basic specs for designing Voltage Regulators for moderns DRAMS? Any link, any article will be helpful.. Regards,
  17. C

    How challenging is it to design a PLL with 50ps Jitter and 100MHz clock output?

    Hello Everybody, How challenging is to design a PLL with 50ps Jitter and 100MHz clock output? Process could be either 0.18u or 0.35u. Regards,
  18. C

    Inductor as Energy Transfer Element in Buck/Boost Converter

    Hello, Can anyone explain(if possible with voltage-current waveforms) that how an Inductor is used to transfer energy in Buck/Boost Converters? Regards
  19. C

    Inductor as Energy Storage/Transfer Element

    Hello, How an Inductor is used as Energy transfer/storage element? Can any one explain usage of Inductor(along with current/voltage waveforms wrt time) for transfer of energy between 2 voltage sources? Regards, Chanchal

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