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    Question about PLL frequency in at-speed test for DFT

    when I do at-speed DFT, I want to using the PLL output as refclk1 for launch and capture clock. But there is a question, if the default PLL output clock frequency is not what I want. How can I make the PLL output clock turn to the right frequecy? Use strap pin? 2. Can I config the PLL register...
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    One question for edge merge for DFT

    when scan chain inserting, set edge merge enable. Why the tool groups all trailing edge clock scan cells first and then groups all the positive edge clock scan cells? what is the exactly reason? Thanks.
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    how to check setup and hold-time between mixed positive and negative edge trigger FF

    1.How can I check the setup time and hold time for a timing path. the first FF is positive edge trigger, but the end FF is negative edge trigger one. 2. The hold time is still depended by clock frequency like normal? Thanks
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    [SOLVED] High Z value in post-layout simulaiton using VCS

    Hi, all when I using VCS to run post-layout simulation, I found some signal is High Z value in the beginning, but when I using ncverilog, there is no such issue. why? In VCS, I found a BUF output is Z value whatever input is 0,1 or X value.There is no force or other reason to make this...
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    Why my ATPG coverage in so low about Multiplier of design?

    Hi, all When I do ATPG, the test coverage is about 25% of some multiplier? why? I found other multiplier test coverage is up to 99%? does bus width and signed/unsigned data of multiplier make sense in here?
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    How to define an internal clock in DC?

    clock mux I just want to define an internal clock in DC. this clock is come from a mux of two input clock then through a combination logic. should be use create_generate_clock? how to use it?

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