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I am doing hdcp. I have a question about hdcpRngCipher implementation.
1 first AN value is generated by using random number seed.
2 other AN value is generated by hdcpBlockCipher sequence and mi,ki.
I want to ask which modules can work during hdcpRngCipher? if the operation mode is same...
I am a hardware engineer.
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My interesting field includes analog circuit design, power circuit design, MCU/ARM/DSP application, stream medai...
verlog simulation using modelsim,there is a error:
Error: F:/myftp/mlf/mlf code/MLF 0116(end)/generic_dpram.v(887): $hold( posedge CLKB &&& re_flagB:1600 ns, WENB:1600 ns, 1 ns );
please tell me how to solve it.
if I write a module as follows:
we know that rom can not be synthesized by dc,so only can be intantiated as above.
but how i deal with this code in dc. because rom general can not be synthesized.
this is a module of my design ,there is memory declaration in it,funtion is correct,now i will syntheze it in order to do timing simulation ,so what do i do with this code and in design analyzer?
thanks ,i am a new asic designer.i need help!
delta-cycle change verilog
if i use posedge clock triger always statement ,but A sigal is posedge change,simulator think it as low level,but that is for synthesis ok?
if Pix_Mux_s1 change from 0 to 1,at the same time memtemp_v1 change frome one value to another value ,then how to assign? it...