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    who can provide hdmi transmitter programmer reference

    who can provide the silicon image 9030 hdmi transmitter programmer reference? thanks!
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    how do I write embedded eeprom?

    I want to let eeprom to store key and eeprom i2c interface do not connect with host interface. How do I write the key into the embedded eeprom? thanks!
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    how to design asynchronous read and write register

    hi, all I want to different clock domain to read and write register file.How do I deal with the metastablility problem? thanks!
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    Questions about hdcpRngCipher implementation

    I am doing hdcp. I have a question about hdcpRngCipher implementation. 1 first AN value is generated by using random number seed. 2 other AN value is generated by hdcpBlockCipher sequence and mi,ki. I want to ask which modules can work during hdcpRngCipher? if the operation mode is same...
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    looking for an English language teacher or a friend

    Hello everyone, I am a hardware engineer. I want to promote my spoken English. And I can teach you Chinese also. Welcome to contact me for language studying or technical interests. My interesting field includes analog circuit design, power circuit design, MCU/ARM/DSP application, stream medai...
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    how to select io pad in asic design

    I design my asic. who can give me some advice about selecting io pad? welcome any doc about this topic. thanks!
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    a problem that simulate using modelsim simulator

    verlog simulation using modelsim,there is a error: Error: F:/myftp/mlf/mlf code/MLF 0116(end)/generic_dpram.v(887): $hold( posedge CLKB &&& re_flagB:1600 ns, WENB:1600 ns, 1 ns ); please tell me how to solve it. thanks
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    kind enough to tell me something about clock design,please.

    I am a beginner. I am design an high-speed AD converter project. I need a 8MHZ clock and then divide it to 4MHz. Introduce some methods or some clock chips. thanks a lot.
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    How to deal with a rom in module code in DC?

    one question if I write a module as follows: module ....... ... .... ... rom (........); .. endmoudle we know that rom can not be synthesized by dc,so only can be intantiated as above. but how i deal with this code in dc. because rom general can not be synthesized. thanks
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    register or latch compare with memory?

    i want to know why people use memory in design rather than register or latch. less area or speed ? thanks
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    who can tell me how i concretly deal with this code ?

    this is a module of my design ,there is memory declaration in it,funtion is correct,now i will syntheze it in order to do timing simulation ,so what do i do with this code and in design analyzer? thanks ,i am a new asic designer.i need help! module regfile( reset_s1, Write_Mem_q1...
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    memory in rtl verilog code

    how to i do ? I write a rtl verilog code, there is a memory in code,if i use design analyzer to compile ,,because i am told that memeory can not be compiled by tools. so how will i do ?
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    verilog simulation question

    delta-cycle change verilog if i use posedge clock triger always statement ,but A sigal is posedge change,simulator think it as low level,but that is for synthesis ok? if Pix_Mux_s1[7] change from 0 to 1,at the same time memtemp_v1 change frome one value to another value ,then how to assign? it...
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    who can give me a standcell lib for synopsys?

    i want to design my idea,so i need a standcell lib for synopsys and verilog simulation lib ,so who can give me thanks a lot.

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