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    Need help with fifo verification

    fifo verification I am new to verification. For verification of fifo, the components required that I have identified are testbench, DUT, bus function model and scoreboard. Is there a difference between testbench and testcase? And can somebody elaborate on the Bus function model for sync fifo...
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    RTL Source code for FIFO - pointers to sources

    rtl code Can somebody suggest if RTL source code for simple designs like FIFO or so will be available on net?. If so suggest some links or sites from where I can download them. Thanks
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    post synthesis simulation of netlist - ncsim

    post synthesis simulation need help in post synthesis simulation of netlist. I am new to this area. Can somebody tell how to go about the simulation of netlist. I tried simulatiing by using ncsim but encountered error in ncelab : CUVMUR instance of design unit unresolved. Also is there some...

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