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    reg determination of rf current density across a rf schematic design

    reg determination of rf current density across a rf schematic design using sonnet Dear Friends, I am in dire need of knowing how to determine the current density of a RF schematic design through sonnet for a RF schematic design that has been done on AWR and EM simulated using microwave office's...
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    doubt regarding common mode swing

    Dear friends, 1) I am having some difficuty understanding why it is necessary to consider common mode input swing for a simple differential amplifier. I know that the common mode gain should be made less. Differential gain should be made high. And in other words, the Common mode signal...
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    doubt regarding current mirror

    I am learning current mirrors. I have a curious doubt. Why is there a need to increase the Rout of a setup to improve the performance of current mirror? Ie. How is Rout and performance of a current mirror related? After all, the reference Ids current on the 1st transistor is copied to the second...
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    problem with bus arbiter priority algorithm

    Hi friends, I have been working very very hard for the past few days on the arbiter part of the amba ahb bus architecture. I am using a fixed priority algorithm for allocating grant to the bus master. I tried simulating the arbiter verilog code on modelsim with the testbench that I wrote. I was...
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    Modelsim:- Waveform does not appear on the wave window

    Hi! I have a perplexing problem and its very irritating. I tried simulating a simple counter in modelsim pe student edition 10.0a. Yesterday the simulation worked and I was able to see the waves in the modelsim wave window after adding the signals to the wave. But today morning after I rebooted...
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    how to increase the height of signals in the modelsim wave window

    As the title says it, I am just struggling to find a way to increase the height of the signals stacked on top of each other in the modelsim (pe student edition 10a) wave window. I tried to "select" the signals one by one and right clicked to check if I can click "format" to change the height...
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    doubt regarding illegeal referrence to net

    This is my code for a priority arbiter of an ahb bus. I am new to verilog. I get some errors as below. ** Error: D:/arbiter.v(116): (vlog-2110) Illegal reference to net "hresp". ** Error: D:/arbiter.v(123): (vlog-2110) Illegal reference to net "hsplitx". ** Error: D:/arbiter.v(157)...
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    simple verilog doubt by verilog beginner

    I have a logic that happens at every rising clock edge. I want to do a simple action. I will tell you the situation. signal a should be 0 as long as signal b is 1. How do i implement this in verilog code other than the conventional if else happening at always @(posedge clk or negedge rst_n) to...
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    any synthesis tool for linux ubuntu 11.04 natty narwhal?

    Hi ppl.. Is there any good synthesis tool for ubuntu 11.04 natty narwhal? I have been using ver 0.9 of lcarus iverilog simulator. But unfortunately it does not support synthesis while the previous version of it does. I can't roll back to the previous version of it as the synaptic package...
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    how to do an action every xth clock pulse?

    Hi guys I have a very basic doubt. I want to know how to do this in verilog. I want to do a particular action every xth clock pulse. How do i incorporate this in verilog? Some ppl say I need to use a counter but lets say I need to do a particular action for every 4th rising edge of the clock...
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    a basic doubt friends

    Hi friends i wrote a piece of verilog code for the following problem statement. (The paper is attached with this thread) Read the SVM implementation paper (Omar Pina-Ramirez, Raquel Valdes-Cristerna, Oscar Yanez- Suarez, “An FPGA Implementation of Linear Kernel Support Vector Machines,” in...

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