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1) Can any one can emphasize on how quickly draw the layouts by referring the schematic. Only Eulers path is the better method ?
2) How to estimate Power bus width
3) How to self learn on skill scripting as its very useful for standard cell layouts(Good material)
Please provide me the details about memory compiler(generator).As per my knowledge compiler generates the cut according to user specifications.What parameters we have to consider in cut generation, like how to consider MUX,WORD,BIT parameters.apart from these three parameters any...
Thank You Mr.erikl
As per my knowledge technology node means it depends on the gate length of the transistor.Suppose i want to design a memory block in 22nm node, What points i want to consider.Any text books enriches these aspects with EDA tool examples.
I have designed a 32 bit ripple carry adder in tanner tool in my personnel computer.
I want to simulate the same design in my laptop.i.e..,I do not want to design again in other machine so how to take the designed file and simulate in another tool.
please tell me the procedure
I have face difficulty in designing of sram design using Negetive word line concept. any body please help me to proceed.any body have complete sram design ( scematic capture) in LT spice....?:???: