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    question regarding timing analysis or slack time

    Yes Below is my timing constraint and also the RTL diagram
  2. D

    question regarding timing analysis or slack time

    Hello everyone. Currently, Im designing a processing element. This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484. I have problem on the timing analysis. The is no setup time and hold time reported as shown below. There is no slack for setup time and...
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    Timing analysis guidance

    Im so sorry I have 21 files. Im designing a systolic array. Systolic array consists of an array Processing Element. So in my design Ive 114 PEs. So my design is very large.
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    Timing analysis guidance

    Hi all. Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below. After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example I need help and guidance based on the experience to improve...
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    Xilinx XPower Analyzer Confidence Level

    @ThisIsNotSam I see Ive generated the SAIF file based on the PAR simulation. I do notice the PAR simulation doesnt give the same result as the behavioral simulation. If I attach the .Saif and glbl file (generated from post place & route model) would it helps you to understand what is...
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    Xilinx XPower Analyzer Confidence Level

    @FvM Thank you for the reply. Does that mean the design is to small for dynamic power analysis? What about the quiscent power? Where would the power come from?
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    Xilinx XPower Analyzer Confidence Level

    Hello everyone. Im using ISE Design Suite 14.7 and Xilinx XPower Analyzer to find the total power for my design. 1. I notice that both the design nets matched and simulation nets matched is not 100%. Why is that? 2. What can be done to increase the confidence level? 3. One more thing, based...
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    Generating SAIF file

    @ads-ee Thank you for the explanation. Ive tried to simulate the testbench and it works.
  9. D

    Generating SAIF file

    I couldnt find .cmd file inmy project directory I do have glbl file. I am confuse which file to simulate. The testbench or glbl file? Please refer to the attachment. - - - Updated - - - @ads-ee I found whats in the isim.cnd file
  10. D

    Generating SAIF file

    Yup for behavioral simulation
  11. D

    Generating SAIF file

    Hello everyone. Im wanted to generate the SAIF file from ISIM. Im using Xilinx ISE Design Suite 14.7 Ive found the method to generate SAIF file. Please also refer to the attach figure. However, there is an error. Please help me to solve the error or any other method to generate SAIF...
  12. D

    [SOLVED] writing to a text file

    ok its working. I at fclose() command. Thank you for all the helps. Can you guys explain to me, why the data is written in the text file when fclose() command is used?
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    [SOLVED] writing to a text file

    Can this command is used in code block? Im using window 10
  14. D

    [SOLVED] writing to a text file

    I am sorry. I do not understand. Can you give some example where can I put the suggested command?
  15. D

    [SOLVED] writing to a text file

    Dear all, How can I write the displayed output in the command prompt to a text file? #include<stdio.h> #include<string.h> int main() { /*declare and initialise variable*/ char message[32][114],buffer[114]; int i=1; FILE *file_in; FILE...
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    wrting multiple substring in multiple text file

    @betwixt Ive tried your suggestion as shown below #include<stdio.h> #include<string.h> int main() { /*declare and initialize variable*/ char message[32][115],buffer[115],t; int i=1; FILE *file_in; FILE *file_out...
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    wrting multiple substring in multiple text file

    Hello. Im writing a C programme that reads the files and trying the save the processed string to other file. So the string is: The inital coding is: #include<stdio.h> #include<string.h> int main() { /*declare and initialise variable*/ char...
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    Weird synthesis error (Xilinx, Verilog)

    Its ok for me the other two output is unconnected But the schematic diagram should detect the sub module
  19. D

    Weird synthesis error (Xilinx, Verilog)

    Yup. The warnings is reported from the complied top module. The ports for the top module is correctly connected (attached). The warnings mentioned previously is about the sub module. From what I can see, the compiler cant detect my submodule (attached) because there were no error for compiling...
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    Weird synthesis error (Xilinx, Verilog)

    Dear all. Im currently synthesizing a design using Xilinx ISE. 14.7 Based on the warning below, it says that ALL the sub module is unconnected. WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical...

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