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    Synopsys VP Virtualizer installation

    Hello guys, I got a problem with Synopsys Virtual Prototyping (VP) Virtualizer installation. Is there anyone experienced with this tool? Thanks.
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    [Channel Coding] Log Likelihood Ratio (LLR) Calculation?

    Hello guys, I'm working on channel coding. Most of decoding algorithm (LDPC, Turbo, or Polar, e.g) requires input data in Log Likelihood Ratio (LLR) format. Would someone please explain to me what component in communication system responsible for this calculation and how it is done? Thank you
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    where signal routing is done in physical design flow?

    I know. But Talus requires power/ground rails to insert filler cells. Once created the rails expand over whole stdcell row to tap with upper power network (mesh, ring).
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    where signal routing is done in physical design flow?

    I'm wondering because in power planning, power/ground rails are created on same layer with stdcells. It will block the routing path if signal routing is done here.
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    where signal routing is done in physical design flow?

    Is signal routing done on same layer with stdcells and macros?
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    Define generated clock during logic synthesis?

    Guys, what's the main purpose of defining a generated clock in logic synthesis?
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    [I2S] Frame sync idle state and start condition?

    Guy, I'm having some ambiguities on I2S standard transaction. What's the default value (0 or 1) of frame sync signal (WS) at IDLE state? How master signifies the slave the data transfer has been started? Is it mandatory for left channel data to be transmitted first? Thanks
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    [SOLVED] FPGA Spartan 6 XC6SLX9 Configuration

    So a FPGA programming circuit is required. I got it. Thank you guys.
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    [SOLVED] FPGA Spartan 6 XC6SLX9 Configuration

    @shaiko, is there a general way to get it done?
  10. Y

    [SOLVED] FPGA Spartan 6 XC6SLX9 Configuration

    https://www.xilinx.com/support/documentation/user_guides/ug380.pdf https://www.xilinx.com/support/documentation/user_guides/ug385.pdf Above are 2 that I've read. I've searched AX309 ALINX board datasheet also but didn't get any results. Thanks
  11. Y

    [SOLVED] FPGA Spartan 6 XC6SLX9 Configuration

    I'm using AX309 from ALINX. **broken link removed** Thanks
  12. Y

    [SOLVED] FPGA Spartan 6 XC6SLX9 Configuration

    Guys, How to download bitstream configuration file into FPGA board using Xilinx Spartan6 XC6SLX9 chip through USB 2.0 cable. I've searched for several days but the results were messing. Can you guys sum up and explain the way for me. Thanks
  13. Y

    [SOLVED] Software set, hardware clear register behavior?

    Guys, In hardware/software interfacing, can I implement a mechanism like this, software write 1 to a bit of register to initiate operation, hardware receive 1, do its job and automatically clear the bit to 0. I see the mechanism of hardware set, software clear in interrupt handling, but don't...
  14. Y

    [General] I2C arbitration at edge or level of SCL

    I know. But which master will win owning the bus in such case?
  15. Y

    [Questasim] why UVM simulation is too slow?

    Yes, UVM simulation uses same stimulus as normal simulation but with UVM added. Thanks Dave, it helps.
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    [Questasim] why UVM simulation is too slow?

    Dave, I'm not specialize in verification. I just want a brief explanation for this. I guest the SVA check, code coverage and functional coverage calculation during simulation slow it down. Please confirm it for me. Thanks
  17. Y

    [Questasim] why UVM simulation is too slow?

    Guys, I'm running normal (without UVM, SVA, functinal coverage, code coverage) simulation and UVM simulation on the same testcase. But UVM simulation takes so much of time comparing with normal simulation. What's the causes of this strange behavior? Please help me to figure this out. Thanks
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    [General] I2C arbitration at edge or level of SCL

    What happens if SDA changes after rising edge of SCL during arbitration process. I mean at rising edge of SCL, both SDA of 2 master are HIGH, so both win the arbitration, but master 1 issues RESTART signal, and master 2 continues transferring data bit. Which master will win the arbitration?
  19. Y

    Multiple I2C master problem

    I dont see problem of high/low clock frequency here. Master B must wait till it detects STOP event on bus to start its data transfer.
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    [General] I2C arbitration at edge or level of SCL

    I2C controller: edge or level trigger design? Guys, With I2C interface design, which design style should be used: edge (flop) or level trigger (latch) based. I see no restriction in I2C specs, latch based design could work fine. Thanks

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