Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
After renew the license, I run the Assura RCX with error. (DRC and LVS are alright) But it is only happened in sparc Solaris machine, it is alright in x86 Linux machine. I use same layout to do the test. Both Linux and Solaris use IC5141 and Assura3.1.7. Please help!
RCX Error message...
When I tried to simulate a invertor with Verilog-XL, I got an two errors
Module or primitive (nmos3) not defined "ihnl/cds0/netlist", 19:nmos3 MN0(.D(Out),.G(In),.S(cds_globals.gnd-));
is similar to (1), but it is pmos3
I am using gpdk for this simulation. Is it the setting problem...
I am a beginner of IC design.
When I use the gpdk to draw a schematic and use spectre to do the simulation, I got some errors in spectre.
si_inp: MN0 is an instance of an undefined model nmos1.
si_inp: MP0 is an instance of an undefined model pmos1.
Then I set the model included files for it...