Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. V

    UCD9240 onboard PMBUS configuration

    Hi, I have an onboard UCD9240 which need to be configured, but it has just one PMBUS interface, and I searched the web, but cannot find a cable supporting PMBUS or I2C. Pls someone tell me where I can find this kind of stuff, thanks a lot!
  2. V

    Misplacement of layers in Altium

    Hi, I was drawing the PCB files in Altium and found something weird. The coordinates of layers seem to be different, as show in the picture. The drill guide layer is not right below the other layer, but a little misplaced. Is there some way to adjust this layer to the right position? thanks a lot!
  3. V

    How to change net in FBGA pinout, Altium

    I'm plotting a PCB file based on a reference design (so no schematic files) and encounter a problem. One chip with FBGA pinout gets the pad inside out through via. Now I want to connect this pad to another place, but just cannot select the via connecting to it and change its net. It seems...
  4. V

    How to creat IP core in Quartus?

    Hi, all! I want to package my own HDL code into IP core (just like NGC or edif files in Xilinx) in Quartus, but cannot find the proper tool. Can anybody help me? Thanks!
  5. V

    Virtex-6 symbol in Altium

    hi, recently I'm doing some PCB work with virtex-6 FPGA (FFG1156), but cannot find the symbol while drawing schematics. The Altium version is 6, is it too old for that? Besides, the virtex-5 symbol in Altium is composed with IO banks, why not in its original form - the square box? Any help is...
  6. V

    Altera embedded multiplier performance

    Hi, all. I implemented a 64-bit multiplier using Altera Quartus MegaWizard Plug-In Manager. The device is cyclone III series. But the classical timing analysis shows that it cannot even meet when tpd=20ns. I wonder why it can be so slow when the device is made with 65nm process, is there...
  7. V

    Quartus signaltap wave record

    Hi, I'm using Quartus 9.0 signaltap for simulation on Altera FPGA. Now I can watch the real-time wave of output PIN in my design, but the wave soon disappeared. So I wonder if signaltap can automatically record the wave for later use. Thanks in advance~~ Regards.
  8. V

    Generate internal low frequency clock?

    My project need to generate a low frequency clock for ASIC use from external high frequency clock input. So there must be a frequency division. As far as I know, it can be implemented with counter(the clock skew and driver capacity are OK?) and PLL, but don't know which one is more...
  9. V

    How to decrease the area of net in DC?

    HI, I just learn to use DC to do the layout for my RTL digital circuits recently, but I find the area of net in reports is really large. Is there some hint to decrease it?
  10. V

    How to add .lib to cadence just like Hspice?

    I'm learning to use cadence, but a little confused about adding .lib tech file to cadence. Is there some simple way to add it just like Hspice? Really appreciate your help.
  11. V

    How to test the GBW of CMFB

    Hi, I want to test the GBW of CMFB in this OTA, but don't know where to separate the circuit and give the input or test the output. Can anybody tell me please? Thanks a lot:)[/img]

Part and Inventory Search

Top