Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. L

    Duty Cycle decision in Design

    ya I have used FF for flip flop.Didn't got u with "falling edge will accepts affects!".Can you be somewhat more elloborative Thanks :)
  2. L

    Duty Cycle decision in Design

    Hi, I just want to know that FF works at posedge of clock and posedge occurs after every Clock period irrespective of duty cycle.So what does this duty cycle effect for a particular design? and what are the factors on which it depends that how much duty cycle to use for a particular design...
  3. L

    Duty Cycle decision in Design

    I want to know how duty cycle of clock is decided for a particular IC design ?

Part and Inventory Search