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    IN NEED OF PREVIOUS VEDA IIT TEST PAPERS(HYDERABAD)...

    Any one to help, at least the topics to prepare. Type of questions asked ? A ny model questions ? please help
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    Standard Cell Library design

    thank you artmalik. as the design is for 90nm library. do my design have specific advantage over NAND gate based design? thanks.
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    Standard Cell Library design

    Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization can we use transimission gate in a standard cell design ? and what are the advantages on nand gate based logic ? the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate...
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    Acde model parameter in Hspice

    Even i face the same problem in 90nm Technology is there any one who could help us Warning: Acde = 1 may be too small in BSIM4 model n12.1 with w=2.5e-07 l=1e-07. Thanks inadvance
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    Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization

    is that transistor level schematic right . Or i should use any gate level one. suggest me
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    Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization

    is that transistor level schematic right . Or i should use any gate level one. suggest me
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    Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization

    AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates suggest me or guid me regading this is the circuit correct ?
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    converting real number to single precision floating point numbe

    use IEE 754 The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation
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    Standard cell characterization flow with Synopsys tools?

    I read the UG ,thank for the information,i finally found the flow to follow on my project which is characterizing a standard cell "asynchronous latch" 1.schematic ----->tool CDesigner SE 2.layout ----->tool CDesigner LE 3.LVS hERCULES 4.RC extraction Star RC...
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    Standard cell characterization flow with Synopsys tools?

    Thank u Sir. where dos the layout extraction come, which tool shuld i use to generate layout view and Abstract view. is it Custom Designer SE and LE
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    How are EDA tools developed ?

    Thanx "hate" so im femilear with java....il go with it..... can u plz give me some reference material or links that would be helpful........
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    Standard cell characterization flow with Synopsys tools?

    tnx for ur reply but Liberty NCX is used to generate .lib file. i want to know how an individual cell is charectarized using synopsys tools. thanks
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    Standard cell characterization flow with Synopsys tools?

    Help me ..! what are the tools use in this flow. i know the cadence flow but couldnt find the replacement in synopsys .
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    How are EDA tools developed ?

    Is It java which is use to develop EDA toola .........?
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    How are EDA tools developed ?

    I am a VLSI student doing my masters in VLSI & Embedded sys. As a final year student i need to do a project. im searching for internships couldn't find any (operchunity)openings. so i am looking to do my own project. My idea was to design a EDA tool for FSM (finite state machines). i.e when i...
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    How to achieve 180 degree exact phase shift by using digital circuits?

    a) Digital clock manager's an inbuilt resource in most of fpga can be configured to get 180 degree phase shift. b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used

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