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I am trying to use the barrel shifter provider by the design ware library
so i am using this code which i copied from the examples coming with the library
in Xilinx ise, when i view the RTL schematic of a module, some buses are connected between the i/o ports and the module and other buses are not connected, what is the reason for this ?
This is an example for what i mean :
Select signal and output are not connected, while the rest is.
I want to build a simple memory module in design compiler
How can I write the VHDL or Verilog code in order for the compiler to build the module using SRAM cells ?
Is there a tutorial or an open source code for a memory module than can be compiled to produce an actual design with SRAM cells ...
I have this line in my code :
MOV PC, r14
It gives an error :
warning: A1608W: MOV pc,<rn> instruction used, but BX <rn> is preferred
So i change it to :
MOV BX, r14
It gave this :
error: A1647E: Bad register name symbol, expected Integer register
help please :)
I am currently learning VHDL, And i understand the difference between behavioral and structural modeling, But i want to know which is better in synthesis (creates a more optimized code) ?, And on what basis should i select a certain model to work with ?
arm assembler Reset_Handle ,__Vectors errors in uvision
I am starting to learn ARM assembly using Uvision, So i am trying to run this code :
AREA Hex_Out, CODE,READONLY
;SWI_WriteC EQU &0 ;output character in r0
;SWI_Exit EQU &11 ;finish program