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  1. C

    Open multi files in verilog testbench

    Fvm, thanks a lot. I have try it and it work well.
  2. C

    Open multi files in verilog testbench

    I have to open a lot of file as file1.txt file2.txt .... file1024.txt How to open these kind of file name with simple method in verilog? Such as use loop for it? thanks.
  3. C

    question about how to use "`include" in verilog

    If I do not write "include" in RTL code. How the tools handle it? Such as modelsim/questa/synplify ?
  4. C

    [REQ]SystemVerilog or VMM material

    Hi, Does anyone can give me any suggestion on SystemVerilog or VMM learning material? Or any group or forum for these? Thanks
  5. C

    [VMM:QUESTION] What's the difference with peek and get?

    how to stop a blocking get vmm Thanks vishalvartak and vinod_cheedella: I got where I make the mistake. Now I have another question. In the program block, I have run the env.run() and I triggered the env.end_test. But the simulation does not stop.
  6. C

    [VMM:QUESTION] What's the difference with peek and get?

    peek + channel + vmm Thanks telantan: But I think the difference is only the data is move out from the channel or not. Why the simulation will be blocked when using the in_chan.get() only? Does the get() will copy the data to tran_data?
  7. C

    [VMM:QUESTION] What's the difference with peek and get?

    try_get vmm Hi, what's the difference between peek and get of vmm_channel? I try to use the code like this: in_chan.peek(tran_data); do_read(tran_data); in_chan.get(tran_data); It works. But if I try it like this: in_chan.get(tran_data); do_read(tran_data); I think the simulation was...
  8. C

    DC error: Syntax error at or near token 'enum_state'

    DC error, enum_state Are you sure the error is caused by this line?
  9. C

    Verilog-Mode in Emacs

    I am using the latest version verilog-mode. But when I use AUTOASCIIENUM. The emacs will cause CPU 99% used and nothing i can. it will never stop. I have to kill it manually.
  10. C

    question about slow.lib and fast.lib on Design Compiler

    I think you should synthesis you design with both. The SDF should have both worst and best case timing in it. To do the sta, you just select which you will use for setup or hold check.
  11. C

    Schematic Level and Block level implementation of Divide by 3 circuit.

    Re: Divide by 3 Circuit this method use the control logic on clock path. I think it is not good for ASIC design. Is it there any other method to avoid logic on clock path? thanks
  12. C

    When do hold time violations occur?

    Hold time Most time try to clear the hold violation, just insert the buffer to delay the signal change.
  13. C

    Simple verilog question

    How can you write this kind of code?
  14. C

    [DC] Determine parameter in set_input_delay?

    I think we should estimate the outside environment for the chip to give the input delay value. I am right?
  15. C

    Gate level simulation: Quaries on simulation issues

    I do not think you can generate test bench by tool. You have to write it by yourself.
  16. C

    Pull up resistor in I2C communication

    I2C pull up I think pull will not cause 'X' except you have multi-driven on this net. If you set pullup on an undriven net, it will not be 'X'
  17. C

    How to insert partial scan in Synopsys DFT Compiler?

    First you can try to find with modules should be scanned or not. Give the list of DFFs should not be scanned such as clock generation, mode select, ... I do not think the tools can analysis all DFFs which should be scanned or not.
  18. C

    How to insert partial scan in Synopsys DFT Compiler?

    I think you can set all the DFFs you do not want to add to scan chain as dont_scan

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