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  1. V

    Multiple Design Available -Cadence Complier Error!!

    Yes TOP is the top module of my design.. Yes its my first design but I'm already using the template script provider by RC..
  2. V

    Multiple Design Available -Cadence Complier Error!!

    I'm don't understand what you mean by multiple design... But this is what I did... set top_module TOP //that is the name of my top module set src_files [list rtl_source/list_of_all_files.v ] //list includes all .v files Then compiled the script though ''rc -f -gui rtlscript_bb.g'' command
  3. V

    Multiple Design Available -Cadence Complier Error!!

    Hi.. Am using cadence to synthesise my design... I'm getting the following error... ''Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [define_clock] : There is no unique design available : Specify a design by using the cd command to change...
  4. V

    FPGA Implementation Verification

    I already have a top module which is the oc8051_top.. okay I will try instantiating the ram into it... And as you told me about the .ucf and .xcf... Am already done with all of that... I just wanted to create the Block Memory as a Post Synthesis process!!
  5. V

    FPGA Implementation Verification

    No I still haven't instantiated it... i have the .coe file with me... i tried generating a blocked memory by choosing this .coe as an Init File... Now I have a blk_mem_gen (.xco file) that is added in the ISE source list... What I did till now is right? If so what should I do next?
  6. V

    FPGA Implementation Verification

    Thanks for your reply!! As far as what I understood, RAM can be initialized through .coe file... But I have difficulty with instantiation process... Any help with that??
  7. V

    FPGA Implementation Verification

    hello... am supposed to implement a 8051 open core (verilog programming) into a Xilinx spartan 3e (xcs3500e) board and verify the implementation with led blink program.. i have implemented the core into the fpga successfully though ISE and iMPACT... My question is how can I load the blink...
  8. V

    Intel 8051 Verilog Code

    Hello. I'm new to this programming world and I need your help. I'm supposed to implement an Intel 8051 core in FPGA(Spartan 3E). So I checked the following websites: 1. Oreganosystems website. They offer codes only in VHDL. 2. Checked opencores.org. It includes verilog code here...
  9. V

    [MOVED] Intel 8051 Verilog Code

    Hello. I'm new to this programming world and I need your help. I'm supposed to implement an Intel 8051 core in FPGA(Spartan 3E). So I checked the following websites: 1. Oreganosystems website. They offer codes only in VHDL. 2. Checked opencores.org. It includes verilog code here...

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