Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. J

    VHDL or Verilog - Which way to go?

    I have an option to choose between Verilog and VHDL to implement logic gates for now. I have checked around, but do not understand what people mean by saying that VDHL is verbose and Verilog is not. I had also read that VHDL is "very deterministic" and Verilog is "only deterministic if you...
  2. J

    Job prospectus

    I would like to know the job prospects if I choose antenna design for my graduate studies? Sorry if this is the wrong place to discuss this. Thanks.
  3. J

    [Moved]: Model parameter values

    Im workinh with BSIM CMG in ADS. Does anyone know how to get the industry parameter values?
  4. J

    [SOLVED] FinFET model for ADS

    I need a FinFET model to perform my simulations on, in ADS. I tried importing the 7nm PTM_MG (LSTP NMOS) into ADS. However, I get a warning stating that level 72 (which is the level specified in the .pm file for nmos) is invalid and hence ignores the line. I am a new user to both ADS and HSPICE...

Part and Inventory Search

Top