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    Using PSL assertion on std_logic_vector in VHDL

    Hello, I just started studying PSL assertion for design verificaion. I am debugging a module which has programmable delay and it seems embeddeding PSL in VHDL code can be beneficial. I want to describe a property of the data path of the module I am working on; I have two std_logic_vector...
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    Inferring Dual port block memory on Virtex-2 part

    I'm trying to infer dual port block memory on Virtex-2 part using ISE 10.1, but I got following error: If I use ISE 13.4 and target other parts (I cannot target V2 on ISE13.4), I don't get the error. Does anyone have experience with this error? How do we infer a dual port BRAM for V2 part...
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    maximum achievable resource utilization in Virtex-4 FPGA ?

    Hi all, I've used Virtex-4 SX35 before. When I used 80%of LUT and 75% of register, it became unroute-able. I've used three BUFGs and a few BUFIOs. In case of V4-Fx100, the maximum I could reach was less than those numbers, and I used more BUFGs. I know it really depends on design, but I...
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    Dual core ARM programming

    Hi all, I haven't done any dual core processing before. How's it different from single core processing? Is OS a must for dual core processor, or can I make the two cores work on different tasks? If you have good reference, could you give me the link please? Thanks, Gongdori
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    Question on interfacing USB-OTG and USB

    Hello, I have a question on interfacing between USB-OTG device and USB 2.0 slave device. If I have a custom board with USB-OTG and a USB 2.0 compliant device, can I setup the custom board to be a master and make them communicate? Or, it is not allowed? Thanks, Gongdori
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    How do I use VHDL write() function to print std_logic_vector type?

    Hi all, I'm trying to use write() function to print out the contents of std_logic std_logic_vector type signals. Can anyone tell me how to do it? I used to use report() function, but recently learned that write() can be used for printing things on a screen... Thanks, Gongdori
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    Does anyone know where "and_reduce()" is included?

    Can anyone tell me which library I need to include to use "and_reduce" function? Also, is the library IEEE standard ? Thanks in advance! Gongdori
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    Displaying a marker in ModelSim using TCL script

    Hi all, I am running Modelsim using TCL script. I wonder if there is any way i can mark on the wave window using TCL script. For example, I want to run simulation for x ns, then mark on the wave window with green or yellow marker (upside down triangle), and so on. Does anyone know how to do...
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    Reference on Adaptive Filtering and parallel filtering

    Hi all, I am trying to understand what Adaptive Filtering is. Can anyone point me to a good reference on it please? From what I read, I learned that it is a filtering technique which uses changing (adapting) coefficients and used for voice processing, etc. It would be great if someone can point...
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    Modelsim error ** Error: (vsim-3601) Iteration limit reached at time x us.

    Hi all, I am getting a modelSim error from post translate simulation. The error says that it reached the max iteration during the simulation. This error does not come out in the behavioral simulation, and persist even if I increase the max iteration value. It seemed that there was a loop in...
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    Timing issue on V4 design

    Hi all, I have a Virtex-4 design with bunch of cores (netlists) The design has multiple clock domains and one of them is 200MHz. When I implemented the design, I noticed that three nets in 200MHz domain did not meet timing. The three nets are from FF in one of the cores, and routing delay was...
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    Xilinx PlanAhead vs ISE ???

    Hi all, I thought PlanAhead was just a floor planning tool, but it seems that it can totally replace ISE. Is it true? I guess internally it calls the same function ISE calls... Does PlanAhead lack any feature ISE has? So far, the only feature I don't see is FPGA Editor. Can anyone tell me...
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    Exception error from Xilinx ISE

    Hi all, I'm using Xilinx ISE 10.1 SP3 and got following error in synthesis stage... "This application has discovered an exceptional condition from which it cannot recover ..." Does anyone have any clue...? Gongdori
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    Does Xilinx XST understand VHDL configuration delcaration?

    Hi all, My VHDL code contains configuration declaration. When I tried to compile the design using SXT, it failed because it couldn't find the component I binded using the "configuration" statement. I wonder if anyone experienced the same thing. If so, how did you fix the problem? Thanks...
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    Questions on Xilinx Virtex-4 power up requirements

    Hi all, In the Xilinx V4 datasheet, there is power supply ramp time requirement (Table 6 in DS595 DC and switching characteristics). It says that the three voltage rails should be ramp up within 0.2ms to 50 ms. (I assume 0V to the 100%?) I wonder where this requirement comes from. Is it...
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    Can anyone give me a reference on Cold sparing

    Hi all, I want to know more on "cold-sparing". Can anyone point me to any good reference please? Thanks! Gongdori
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    Powering FPGA with 2 layer board?

    Hi all, I want to build a simple circuit with a FPGA. I initially thought about building 4 layer board, but later learned that it would be very expensive. The FPGA I want to use requires 3 voltage rails... I wonder if it would be possible to be done in 2 layer board? The circuit will have 1)...
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    Dynamic range and SFDR of DDS

    Hi all, I have a design question on DDS. I designed a DDS in VHDL. The dynamic range of it is about 108dB, but SFDR is about 64dB. I wonder if it makes sense to have the dynamic range of 108 DB, while SFDR is only 64dB... When I designed it, I tried to fully utilize one block memory. That's...
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    Hilbert transform and down sampling

    Hello, I am a DSP newbie and have question about downsampling after Hilbert transform. I have a real signal coming into the system and i am going to use Hilbert transform FIR filter to make analytic signal. Then, since I have only one sided spectrum, I am going to down sample it by 2. And...

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