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  1. wadaye

    Is there some dediacted palce tool for ASIC?

    Hi all: As I know, we have dedicated floorplan tool, route tool, but is there some dedicated palce tool? Not included in p&r tool, like astr0, se, apllo?
  2. wadaye

    Are there some lint tools for vera or e?

    Are there some lint tools for vera or e? Except the compile tools from syn0psys and veris1ty? How about the speed, if the answer is yes. wang1
  3. wadaye

    Is the ACS command of DC used in your company?

    Synopsys provided ACS commands, and they say these command are useful. But as I know no company use the ACS commands, are your company uses these commands? wang1
  4. wadaye

    [Help]: How can calculate the coverage with more than 1 tb

    Hi all: It's hard to test the a complicated verilog design with only one testbench. So when I use more than one testbench fils to verify my design, how can estimate the coverage? Is there some simulation tool or coverage tool can do this work? wang1
  5. wadaye

    Which P&r tool will get better result?

    zbwqiang After Logic Synthesis, we can use Jupiter+Astro, or Encounter to do physical work, which will get better QoR? Pls be detail! wang1
  6. wadaye

    Can I do IPO post-layout in DC?

    Hi all: Can I do IPO post-layout in DC. If can, which tcl-command should I use, and what data should I input?
  7. wadaye

    Can I do AMS with HSIM & NC?

    Recently I have to do AMS of a SOC chip, but I only have HSIM and NC, can I do AMS with them? :?:

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