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Input bits are continuous but I need add Header for each and every time, so only I`m missing input.
I designed this by taking Buffer but this is going Overflow after some time.
I had continuous input bits and for each and every 20 bits of input I need to generate 5 bits of Header to...
I am designing "time interleaver" for DVB-T2, which is require large memory to be store before interleave.
Means, 32400 values in a one row and like that 1024 column of data need to be store before doing operation.
32400 rows, 1024 columns and each location of 17-bits wide.
This is code for finding CRC for all combination of inputs. I cheked this before synthesis which is working fine but after synthesis giving error as bellow.
I attached image of DVB-T2 "Bit-Interleaver" in that columns and Rows are given. This is for 16-bit QAM and length is 64800-bits. This divided into 8100 rows and 8 columns. The data coming from previous block is "one Bit per Cycle". First bit store in 0th location like that First...
I`ve files which are contain plenty addresses(integers 16-bit). Each file contain lakh together integers. I need to store and used in a program.
I`m worry about memory of FPGA whether which sufficient or not. Because each and every model has many memory blocks used...
I`m designing DVB-T2 using VHDL for my post graduation as a final year project.
I designed upto parity interleaver in BICM, but I finding a difficulty in design of "Bit interlaver". I request you to pls guide me how to design Bit inerleaver part. Interleaver does...
This code for Parity interlever in DVB-T2. I assign valuesusing case statement but which is also not going to synthesizing and taking long time.
case x is
when 32400 => index <= 32400 ;
when 32401 => index <= 32490 ;
when 32402 => index <= 32580 ;
when 32403 => index <= 32670 ;
It has reading external file and applying different values. Need code in VHDL pls help out.... It work fine in modelsim 6.5.
I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing.
Ex: signal Buf1(64799 downto 0);
signal Buf2(64799 downto 0);
What is the alternative to this problem and how to design such complected buffers..