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  1. W

    rate mismatch between input data to output data

    Hello, I need to send 32208 bits of serial data within the 32128 clock per bit of input in VHDL..... How to do this rate change between input and output...? output has more data than input....
  2. W

    eliminating intermediate delay

    Hello, Input bits are continuous but I need add Header for each and every time, so only I`m missing input. I designed this by taking Buffer but this is going Overflow after some time. Ex: I had continuous input bits and for each and every 20 bits of input I need to generate 5 bits of Header to...
  3. W

    solution for large memory requirement for FPGA

    Hello, I am designing "time interleaver" for DVB-T2, which is require large memory to be store before interleave. Means, 32400 values in a one row and like that 1024 column of data need to be store before doing operation. 32400 rows, 1024 columns and each location of 17-bits wide. 32400...
  4. W

    How to increases Maximum operating freqency

    library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity map1 is port(clk:in std_logic; reset:in std_logic; code_rate:in std_logic_vector(3 downto 0); mod_mode_sel:in std_logic_vector(1 downto 0); N_ldpc:in std_logic_vector(15 downto 0); input1:in std_logic...
  5. W

    Error in Post-synthesis, ModelSim

    This is code for finding CRC for all combination of inputs. I cheked this before synthesis which is working fine but after synthesis giving error as bellow. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all...
  6. W

    how to implement interleaver in FPGA

    Hi.......... I attached image of DVB-T2 "Bit-Interleaver" in that columns and Rows are given. This is for 16-bit QAM and length is 64800-bits. This divided into 8100 rows and 8 columns. The data coming from previous block is "one Bit per Cycle". First bit store in 0th location like that First...
  7. W

    Memory Limitations of FPGA

    Hi...................... I`ve files which are contain plenty addresses(integers 16-bit). Each file contain lakh together integers. I need to store and used in a program. I`m worry about memory of FPGA whether which sufficient or not. Because each and every model has many memory blocks used...
  8. W

    problem in design DVB-T2 Bit Interleaver.....

    Hi...... I`m designing DVB-T2 using VHDL for my post graduation as a final year project. I designed upto parity interleaver in BICM, but I finding a difficulty in design of "Bit interlaver". I request you to pls guide me how to design Bit inerleaver part. Interleaver does...
  9. W

    taking too lengthy time to synthesize

    This code for Parity interlever in DVB-T2. I assign valuesusing case statement but which is also not going to synthesizing and taking long time. case x is when 32400 => index <= 32400 ; when 32401 => index <= 32490 ; when 32402 => index <= 32580 ; when 32403 => index <= 32670 ; when...
  10. W

    Need equivalent code VHDL testbench for Verilog testbench

    It has reading external file and applying different values. Need code in VHDL pls help out.... It work fine in modelsim 6.5. module Buf_tb; // Inputs reg clk; reg reset; reg [15:0]K_ldpc; reg [0:0]input1; integer file; // Outputs wire [0:0]output1; // Instantiate...
  11. W

    alternative for variables used in VHDL coding....

    Is their any why to avoid lengthy variables or signal used in the VHDL.....?
  12. W

    problem in synthesis

    I`m designing interleaver so need to store 64800 bits and also do circular shift using formula and output those values bit by bit....
  13. W

    Xilinx not synthesizing- taking long time

    Hi, I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing. Ex: signal Buf1(64799 downto 0); signal Buf2(64799 downto 0); What is the alternative to this problem and how to design such complected buffers.. Thank you.. Vinayak

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