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  1. S

    Can we make a LATCH from FLIP FLOP

    Hi, if the clock frequency is exactly equal to (setup+hold) time duration then the FF and latch. Thanks & Regards, Sri. Added after 1 minutes: Hi, if the clock frequency is exactly equal to (setup+hold) time duration then the FF and latch are same. Thanks & Regards, Sri.
  2. S

    Need info about designing clock dividers

    Re: clock dividers Hi, T-FF will be a clock divider. Input to T-FF is logic-1 always Output of T-FF is always toggled w.r.t input clk. the frequency will be half the input clk. Thanks & Regards, Sri.
  3. S

    The differences between HDL and HVL

    Re: HDL vs HVL Hi, HDL is used for RTL design. HVL is used for RTL Verification(Random Verification). Thanks & Regards, sri
  4. S

    how to run the perl file in the redhat linux 7.2

    hi, i am quit new the linux environment .i need information regarding how to run the perl file in redhat linux 7.2 . is perl software is inbuilt or i have to ldownload from the net and load the software. if possible give me command for rnning the perl program in linux. thanks...
  5. S

    information needed regarding regression testing

    hi, how we can go for regression testing in case of specman elite what will the procedure to follow. with regards, srik_naidu Added after 3 minutes: hi, here what will be the batch mode.can anyone give me an idea how the process will be. thanks in advance, with regards, srik.
  6. S

    information needed regarding regression testing

    hi all, i need information regarding regression testing.these are my doubts, what will be the regression testing,when can we use that particularly in case of using specman elite . thanks in advance, wth cheers, srik
  7. S

    false path in constraints

    hi, false paths are not related with the clocks in the design. with regards, srik.
  8. S

    How do you synthesize a latch?

    Latch synthesis hi, in case of vhdl:- if en='1' then q<=d; end if; with regards, srik.
  9. S

    Anyone used "OCP" to design SoC?

    hi, try to get the technical info from www.ocpip.org/faqs. which is very helpful. with regards, srik-naidu
  10. S

    Xilinx Startup_virtex4

    hi, just now i was started using xilinx 7.1i. i got some problems. with regards, srik.
  11. S

    ModelSim SE 6.0 and systemC

    hi, go through the modelsim6.0 reference manual you can find this manual in help option of menu. with regards, srik.
  12. S

    How to Write "Literate" FSM in Verilog HDL?

    hi, refer to verilog hdl by samir palnitkar it will helpful to you. with regards, srik.
  13. S

    Problem with delay in interface that doesn work at 150Mhz

    about the delay hi, use buffer at the input and output of the design. with regards, srik
  14. S

    Syntehsizable VHDL Code

    hi, introduction to vhdl by douglus perry is the good book for vhdl synthesis. with regards, srik.
  15. S

    The comparison of ASICs and FPGAs

    ASICs Vs FPGAs hi, in case of fpga alot area is wasted but in case of asic it is not like that. fpga is reprogrammable but asic is not. with regards, srik.
  16. S

    What results in the Negative Setup Time?

    hi, Setup time is the minimum time that an input must stabilize to its logical level before the active edge of the clock in order to assure that that input is correctly recognized. If a circuit has a negative setup time, this means that the input can change after the clock edge and...
  17. S

    what's the major difference between structure ASIC and FPGA?

    hi, from technical point of view fpga is reprogrammable while asic is application specific and alot of area is wasted in fpga compared to asic. with regards, srik.
  18. S

    What is Equivalence Checking?

    hi, Its application is by comparing RTL vs RTL, RTL vs gate, gate vs gate after design changes. it is helpful to find the synthesis tool problems. with regards, srik.
  19. S

    0.18 um technology - what does it mean

    hi, Technlogy is nothing but channel width with regards, srik.
  20. S

    what is formal verification

    hi, formally verification needs to verify the written properties(specifications). using psl/sugar,vera we can write properties. with regards, srik.

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