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    how to solve the problem: if setup time is not enough?

    HI, it's an IC interview question, can anyone give me a perfect answer? When your design's setup time is not enough, what will you do? How to design a 5.5 frequency divder with some simple CMOS transistors?
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    what dose it mean -- Fading and erosion?

    I heard a lot of guys say the words regarding DSP system, can anyone explain them? fading? erosion?
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    how to generate *.syn file

    *.syn file contains RTL hierarchy and used for DC synthesis. It's error-prone to write it manually.
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    How to set VCS working directory

    my codes need to read a vector and I put the vector file in the codes folder, but when I compile it with VCS, it always told me: How can I do to solve it?
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    Booth algorithm hardware implementation

    booth algorithm vhdl code Anyone knows about Booth algorithm? It's great help to hardware multiplier, here I got an example which can be your reference. Also, can somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate"...
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    How to make a SystemVerilog Class to read a text vector

    system verilog read file How to make a SystemVerilog Class to read a text vector and how to sync it with the global clock? read every byte per cycle I have tried to write one but it seems not work... can anyone give me a hint on that? class #(parameter File_Name =...
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    [help]VHDL translated to verilog, hard stuff?

    Somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate". Thanks! ------------------------------------- -- Define data width -- ------------------------------------- package mypackage is constant NBITS :natural := 7...
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    What is Elaborate in ncsim?

    ncsim elaborate I have seen many times the term of Elaborating the design, but I cannot catch it, can anyone explain it to me?
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    How to write a file logging for testbenches monitoring

    Here is my segment codes: ////////////////////////////////////////////////////////////////////////////////////// .... assign err_flag = !(pro == pro_T); //err flag logging to file initial begin integer fp = $fopen(file); if (err_flag) $fdisplay(fp, " ---- pro is %h; | pro_T is %h; |...
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    [Dis] How to quickly verify data intensive RTL by using SVA?

    I want to verify a simple DSP RTL codes, can anybody suggest a good way by using sva? here is example: module test_assertion( data1, data2, sum ); input [11:0] data1; input [11:0] data2; output [ 5:0] sum; logic [12:0] d1; logic [11:0] d2; logic...
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    systemverilog questions on how to write a class

    system verilog questions Hi, guys! I want to write a class in systemverilog which can implement calculate generic array's sum, product. eg. class arth_oper; .....; endclass module test_class(); .... //when I call it int a [] = {1, 2, 3, 4}; int b = a.sum //b = 10; int c = a.product; //c = 24...
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    How to translate complex algorithms to RTL

    We need to do a project to make a voice recognition chip, now we have a verified algortihm and some other related ones. What we should do now is to translate these complex algorithms to RTL(Verilog discription). The algorithms may come from DSP chip which is based on C or ASM programming. I got...
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    what your viewpoint on ESL?

    any comment is all welcomed. talk about your viewpoint on the concept and the tools of ESL nowadays or future.
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    need your suggestion on Analog Books

    A newbie wants to learn analog design and dosen't know where to start and what book to take. Could anybody recommand some best books? I may purchase them from Amazon.
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    could anyone recommand a MIPS debug tool?

    just for studying MIPS assembly coding. WinMIPS64 is not so good!
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    [help]can anybody help me with this final test problem

    Please refer to the drawing uploaded Thanks in advance!
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    any tool can fully support systemverilog?

    I mean systemverilog3.1a standard. I found Models!m could never do it good. can anybody suggest some better?
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    Looking for tutorials to learn using DC2000.05

    [Help] How to learn DC? Dear all, Before that I am an FPGA designer, familiar with VerilogHDL. Now I was told to make the design into ASIC so I have to learn DC2000.05, however I found it's very difficult to learn, even there isn't any tutorial in the software. How do I start? I don't know how...
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    [help]what's the problem with my verilog program?

    range must be bounded by constant expressions. I made a program but when it prompts errors when compile. Range must be bounded by constant expressions function [8*`w-1:0] cast; input [`w-1:0] data_i; input [2:0] addr_i; integer index; for(index=0; index<8; index=index+1) if(addr_i ==...
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    SystemC will die? Why, can anybody give an explain?

    wesam gobran+ ieee Years ago lot of people said systemC would be the perfect replacement of VHDL & verilog and it's gonna to be next generation efficient HDL. However till now, SystemC has not been in the HDL stage even as a minor role. Synopsys declared that they would abandon SystemC EDA...

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