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  1. T

    Installing vitis on a low specs-pc

    Hi, In Xilinx documentation https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245, the minimum requirement for installing Vitis is 32 GB memory. My pc is a hp ProBook 450 g3 i7 6500 with an 8 GB RAM DDR3. Would I be able to synthesize...
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    [SOLVED] Initializing Xilinx BRAM with image pixels

    Thank you all for you replies, I solved the problem
  3. T

    [SOLVED] Initializing Xilinx BRAM with image pixels

    I already did the first two steps, for the last step I tried to display the values of the matrix in the command window but I can only display correctly few rows at a time correctly,I was wondering what may cause this problem ?
  4. T

    [SOLVED] Initializing Xilinx BRAM with image pixels

    Let's say I use matlab, how can I do that ?
  5. T

    [SOLVED] Initializing Xilinx BRAM with image pixels

    My question here: is there anyway to convert an image file into coe file ?
  6. T

    [SOLVED] Initializing Xilinx BRAM with image pixels

    Thank you for your help, but please next time don't lecture me.
  7. T

    [SOLVED] Initializing Xilinx BRAM with image pixels

    Hi, I would like to initialize Xilinx BRAM (ROM) with image pixels, any ideas ? cheers,
  8. T

    Intialization of SDRAM DDR2 memory in Xilinx tools

    why would I still need read images from the flash and write to RAM ?
  9. T

    Intialization of SDRAM DDR2 memory in Xilinx tools

    what about flash memory ? I am using digilent Atlys board
  10. T

    Intialization of SDRAM DDR2 memory in Xilinx tools

    I would like to know how can initialize the content of DDR2 memory using xilinx tools ? my purpose is to load to static images to the memory before starting its operation, meaning initialzing different memory locations with different pixel values.
  11. T

    Frame buffer controller with dual_clock FIFO

    I splitted the memory into two sections so that each of the ports has its unique address space, so there is no overlapping here, I didnt use two separate block of RAMS beacuase I'm trying to save the resources here
  12. T

    Frame buffer controller with dual_clock FIFO

    I am trying to build a frame buffer controller to control two video feeds coming from two stereo cameras simultaneously on digilent Atlys board (spartan 6). the buffer is composed of a true dual port memory with two ports A and B to store the two video feeds the data is read from either ports...
  13. T

    Monitoring different clock domains in chipscope pro

    Some gudies about chipscope pro ?
  14. T

    Monitoring different clock domains in chipscope pro

    I have a multi_clock design, Is it possible to display the different clock domains on chipscope pro tool and how ?
  15. T

    Counter Preload by any given values

    I'm sorry what is exactly the problem in this code ?
  16. T

    Counter Preload by any given values

    use a synchronous counter with reset value 5
  17. T

    Strange behaviour of Standard dual-clock FIFO

    I am trying to store video feed from dual-port memory inside it
  18. T

    Strange behaviour of Standard dual-clock FIFO

    Thank you very much, I think it's much better if I implement my own FIFO
  19. T

    Strange behaviour of Standard dual-clock FIFO

    I'm not sure i'm following you, but can you tell me why_data_count is incrementing even though rd_en = 0, this is my testbench code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with...
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    Strange behaviour of Standard dual-clock FIFO

    I'm using the Xilinx core generator to generate a dual-clock FIFO in standard read mode, the simulation in Isim shows a strange behaviour, the first two writings are skipped as indicated by the wr_data_count output can somebody please tell me what are the possible reasons for such behaviour ?

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