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sti layout cmos
Does anyone have any documentation or web links on sti stress? I'm particularly interested in where to position bulk connection/substrate taps. Everything I have read so far does not cover this area.
On larger processes I have layed out devices with say an M=6 in the...
parasitic diode extraction
Is it possible to output diode parasitics the same as RC using calibre PEX without having to explictly add them to the schematic?
I have a mos device with its source node connected to the bulk and interested in the what the extracted diode is from the nwell to the...