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  1. D

    Programming Lattice iCE40LP

    Well Lattice keeps its 'settings' in SRAM but it also includes non-volatile memory and it has ability to 'boot' its SRAM configuration from the non-volatile memory. So on my original question. Anyone knowing how to program the iCE40LP non-volatile memory without Lattice diamond programmer? Dora
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    Programming Lattice iCE40LP

    yes I would like to use non-volatile fpga as don't want to put external memory. Startup behaviour is not very critical for this project, but you mean non-vlatile fpgas configure itself faster? Dora
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    Programming Lattice iCE40LP

    Hi Gents, @Tetik Thanks for the remark. I have selected 32QFN part with 0.5mm pitch which should be OK. Now I see they have 0.35mm pitch componenets which indeed we have to keep far from. @ads-ee Yes I have study this document and from what I have undestood there are not clean definition...
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    Programming Lattice iCE40LP

    Hi All, edaboard user pointed me to Lattice iCE40LP low end FPGA chips as an inexpensive replacement of bigger CPLDs. Chips looks really interesting to me even though they require 1.2V, 2.5V and eventually 3.3V power supplies. I decided to give them a try. The chips includes nonvolatile...
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    [moved] clock domains crossing

    Hi ads-ee, Thanks for the code. Meanwhile I have been implemented my version which seems to work fine. Typically the PCM interface is driving outgoing data on one of the clock edge and sample incoming data on the opposite edge. So I had to use dual clock edge design anyway. For this test I...
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    [moved] clock domains crossing

    Hi ads-ee, Well XC95144XL can be with 81 or 117 I/O pins. So it seems to me still some pins flexibility for a certain amount of macrocells. Yes please share your code. It will help me. Thanks Dora
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    [moved] clock domains crossing

    Hi ads-ee, Thanks. I will cehck it. Actually I was disapointed from the fact Xilinx has no 144 cells CPLD with smaller amount of pins. Dora
  8. D

    [moved] clock domains crossing

    Hi ads-ee, What you describe looks about the same complexity as what I had in mind. Aparently you are strongly against using both clock edges even in the very simple form I explained. Few additional questions. 1. What is the tool you have used to draw the waveforms? 2. I plan to validate...
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    [moved] clock domains crossing

    Let me explain what I have in mind: Yes I am thinking about two 'alywas' blocks for the two CLK1 edges. They are looking for the positive edge of FSYNC2 At least one of this blocks should detect the FSYNC2 posedge reliably as either positive or negative edge CLK1 will hit at the stable FSYNC2...
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    [moved] clock domains crossing

    Hi ads-ee, Thanks for the clarification. On another idea. If I manage to sample FSC2 by the CLK1 then I think I have solve the whole task. FSC2 is about one CLK1 period long CLK1 is abpout 50% duty cycle. What I know is that I will have at least one CLK1 edge (positive or negative) in a...
  11. D

    [moved] clock domains crossing

    Hi ads-ee, Yes I know what you are saying and I tend to agree with you. If the BOM cost appears to be accetable we will rather go to external oscilator solution. Thanks Dora
  12. D

    [moved] clock domains crossing

    Hi pbernardi, I see the idea. In my opinion the only weak point is at >4) On next FSC1, you will move the data from 2nd buffer to a shift register, but ONLY if no transfer is being done. This shift register trigger the transmission by FSC2, so: What will happen if FSC2 occurs at the same time...
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    [moved] clock domains crossing

    Hi pbernardi, Yes 1,2 frames latency is acceptable. Can you elaborate on your idea. How to garantee that the second bufer is never written on the transfer in CLK2/frame_sync2? Thanks Dimitar
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    [moved] clock domains crossing

    Hello, Well both PCMs has a separate data_in and data_out wire so it is full duplex comunication. From the technical perspective the issue for the both directions is exactly the same so we can think of a solution for one of the directions only. In PCM/TDM all is serial. So we have 1 wire for...
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    [moved] clock domains crossing

    Hi ads-ee, Well I actually may have faster clocks. In order to simplify the question I have presented it not in its pure form. Your response makes me think I better explain the main task. What I am actually trying to do is to glue two PCM (TDM) interfaces. Both PCMs have: -256KHz clock...
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    [moved] clock domains crossing

    Hi ads-ee, Thanks for the response. f1 and f2 are the same but not derived from the same source. So yes they can drift a bit. if f1 is 100ppm faster than f2 at 10khz I will have to miss 1 word each second. if f2 is 100ppm slower than f2 at 10khz I will have to repeate 1 word each second. I...
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    [moved] clock domains crossing

    Hi Gents, I have the following engineering issue which I would like to solve using CPLD in Verilog. I have a 16 bit data bus and I get data stream on this bus coming at f1=10KHz clock. I want to pass this data stream to another asynchroneous f2=10Khz clock domain. Each coming word in the f1...
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    EDGE/HSDPA over UART/SPI

    Hi FvM I will try to get some of the Cinterion datasheets. I've seen modules with 4mbit/sec UART which I may interface with our fast UART. BTW I don't have big experience with those data modems. Does it mean that I can fully control and use those modules without the USB interface and...
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    EDGE/HSDPA over UART/SPI

    Hi All, I plan to integrate 3G/4G module to our system. I have noticed that most if not all 3G/4G modules are having USB for the fast data services. We don't have USB in our CPU system but we have 5mbit/sec uart. Does anyone has experience with SIMCOM/TELIT/WAVECOM/Cinterion 3G or 4G modules...
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    "Digital Media Software" from TI

    Hi all, Is there somone knowing what "Digital Media Software" from TI incldes? Can somone share it with me. Please PM Thank you! dora

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