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  1. S

    Working culture within intel

    Hello: I welcome your inputs on working culture inside Intel. What is pro and con of the rank and file scheme (also known as R & R)? Given other alternative, would you join this world biggest semiconductor for your career development. I really appreciate your sincere and unbiased...
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    intel freezed all new hiring?

    hi, can anyone comment on this? My lady friend succeeded in the job interview and had been convinced by the hiring manager that she is interested in getting her service in her newly established team. Then few weeks' later (lately), the hiring manager called and told her that she needs her to...
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    Installing LINUX Distribution updates files

    Hello Linux PlayMate: I have a question, in fact, a trivial one. Not sure where to start. Hope you can give me a few spare time of yours; guiding me through the process of updating my Linux laptop. Let's start. I have a laptop installed with SUSE 9.1 pro from the official disk. I am...
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    ModelSIM User Conference 2005 Presentation Slides (PDFs)

    Follow the URL link **broken link removed** regards, Siew
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    Assertion based methodology and tool user manual

    hello. I am interested in learning and using assertion (PSL, SystemVerilog) on my next verification project. Can you share with me your success story (not from tool vendor!)
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    [REQ] User manual for @HDL, RealIntent, Cadence PSL tool

    Any user manual, tutorial, training on using these PSL (property based language) tool from companies : @HDL, Safelogic, Cadence Incisive, RealIntent.
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    [REQ]TransEDA VN-SPEC user manual

    TransEDA VN-SPEC --- specification based verification tool. any user manual?
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    Discussion: Specifying timing constraint on FPGA design

    hello. I am newbie to FPGA technology implementation. Reading papers on static timing analysis, it appears to me that implementing a design (into an FPGA) without specifying the timing constraint (arrival time, required time, false path, multi-path, ..) will result in a NOT-SO-GOOD performing...
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    Suitability of EDA Windows tools for SoC (large design)

    Helo. Please, I hope this is NOT a no-brainer discussion. I would like to know if any those IC power house is running Windows based EDA for their IC/SoC design. I do know that most EDA tool (except Synopsys notably) supports multi-platform tool. I am Windows power user and have been using...
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    Who uses SynaptiCAD products

    tutorial on synapticad Hello. I would like to who ( in this forum ) uses SynaptiCAD products. I am using its TestBencher Pro to automate my VHDL testbench. However, I could not simulate the project (using the tutorial example) in ModelSIM from Testbencher Pro (version 9.0p). Am i missing...
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    question regarding Synopsys VERA

    Vera hehe. I have some question regarding Synopsys VERA. How do I execute VERA Testbench? Do I need only software VERA 5.1.1 from Synopsys FTP in order to execute VERA coded testbench? Or, I will need to install Synopsys VCS version xx and VERA 5.1.1 software. please clarify. Does Synopsys...
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    Forte Design QuickBench release 6.1 License request

    I need license for Forte Design QuickBench release 6.1 or greater. Can you help
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    ModelSIM training material

    modelsim training Hello. I am looking for ModelSIM training materials that is used for ModelSIM Basic and Advanced Training Classes. I did gathered few ModelSIM PowerPoint SLIDES from ModelSIM User Conferences 2002 and 2003. I think some formal training material on the tool is USEFUL and...
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    Safelogic_ModelSIM Add-on tools( Monitor , Verifier )

    Hello Can someone share these files. regards, saholiang@yahoo.com
  15. S

    transeda_verification.navigator.2002.01 onwards

    Hello. Wondering if I could share your license for VN2002.01 products. regards saholiang@yahoo.com

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