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  1. F

    software reset & hardware reset???????

    in fact hardware reset sometime is produced by software, for example mcu send the reset signal to gpio which connect some chip reset pin.
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    who can provide hdmi transmitter programmer reference

    who can provide the silicon image 9030 hdmi transmitter programmer reference? thanks!
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    how do I write embedded eeprom?

    I want to let eeprom to store key and eeprom i2c interface do not connect with host interface. How do I write the key into the embedded eeprom? thanks!
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    Questions about hdcpRngCipher implementation

    Re: hdcp thanks for your reply. you means LM0 is lfsr module, BM0 is block module in hdcp cipher structure? CM0 is block module and output function? the right usage of hdcprngcipher : 1 let CM0 work for some clocks to produce an after power on ? 2 let CM0 work 56 clocks to porduce an after...
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    how to design asynchronous read and write register

    thanks for all reply. my application is cpu write and read data of configuration register at some clock frequency, but hardware engine use these configuration data as input signals. 1 double clock for control signals, these control signals including write and read enable ,not including...
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    how to design asynchronous read and write register

    hi, all I want to different clock domain to read and write register file.How do I deal with the metastablility problem? thanks!
  7. F

    looking for an English language teacher or a friend

    I have added you to my friends list but I do not know when you will be online. I will be online at Beijign time 19:00 to 24:00.
  8. F

    looking for an English language teacher or a friend

    Thanks for your reply. I will contact you soon.
  9. F

    Questions about hdcpRngCipher implementation

    I am doing hdcp. I have a question about hdcpRngCipher implementation. 1 first AN value is generated by using random number seed. 2 other AN value is generated by hdcpBlockCipher sequence and mi,ki. I want to ask which modules can work during hdcpRngCipher? if the operation mode is same...
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    looking for an English language teacher or a friend

    Hello everyone, I am a hardware engineer. I want to promote my spoken English. And I can teach you Chinese also. Welcome to contact me for language studying or technical interests. My interesting field includes analog circuit design, power circuit design, MCU/ARM/DSP application, stream medai...
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    what's the meaning of "set_output_delay -min -1.0 ...&q

    set_output_delay example set_output_delay -min -min= Thold -Tc Thlod is the hold time of flip-flop. Tc is output of chip minimum path delay.
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    Where to start learning ASIC sensor design?

    Sensor IC's Optoelectronic Devices: Advanced Simulation and Analysis (Hardcover) by Joachim Piprek (Editor) "For the theoretical analysis and modeling of semiconductor lasers, it is desirable to have access to reliable absorption/gain and refractive index calculations
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    How can I do power consumption estimation with VCD file?

    you can use vcs simulation tool to do power consumption estimation with VCD file. you can also use primepower or power compiler.
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    H.264 Decoder IP core

    I can not find it on internet, so write one yourself.
  15. F

    Ask about the timing in FPGA...

    dragon_boat's answer is easier for u. you can divide ur frequency with a rather large number your chip supports. then delay 1s is easy by timer. good luck
  16. F

    i want to begin learning cpld

    can someone explain how cann I begin to learn the FPGA development with Altera's chip. how to do it setp by setp? I have some basic knolodege for microcontrollers. Thanks. bye
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    how to synthesis a clock with multi frequency?

    if it is 2 asynchronous clocks, it is your design problem, in dc, you set_false_path. if it is asynchronous clocks,let dc to process timing , same to one clock.
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    What does the "trip-point" mean in DC

    Vendors characterize the libraries after SPICE simulation. They use certain trip points on the SPICE results to determine the transition of the cells. Therefore transition numbers are associated with trip points. If you have multiple libraries and they come from different vendors, you might...
  19. F

    What is Pausable clocking?

    always @ (posedge clk or negedge clear) if(!clear) clk_2 <= 0 ; else if(!en_n) clk_2 <= ~clk_2 ; else clk_2 <= clk_2 ;
  20. F

    Does RESET signal need a buffer tree?

    backend tools can automatically deal with reset , eg socencounter.

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