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  1. R

    What is a CRRP and its advantage?

    Re: CRRP Hi, I will try to put in a different way CRPR stands for Clock Reconvergence Pessimism Removal. While doing FF-FF timing analysis, we are adding up the common clock path twice for the data path and the clock path. This leads to pessimistic results. When we use the CRPR switch we...
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    Questions related to Physical design: kindly help (Part 4)

    Re: Questions related to Physical design: kindly help (Part Please find my answers below 26. how to do ILMs for timing optimization? A) ILM stands for Interface Logic Model. When faced with running STA on huge blocks we use ILMs of child blocks to run top level STA for better run times. ILMs...
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    What is done in CTS stage of EDA tools ?

    Re: CTS Hi, CTS engine also works on fixing max tran and max cap violations, reducing the clock insertion delay and balancing the skew as well. Best Regards, Rakesh
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    Global routing and is detail and global router the same?

    Re: globalrouting Hi, In global routing stage the tool just assigns particular a route to a particular GRC and the layer name. Routing doesnt take place inGR. Ony during the track assignment detail routing the routing takes place. We have options to use non-preferred routing in some special cases.
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    Power analysis using JupiterXT

    jupiterxt guide Hi Siva, JupiterXT has a power analysis utility called PNA(Power Network Analysis). Eventhough it is not sign-off it is a useful one to do some analysis like IR Drop values, voltage maps during intitial stages. For your case you can do a comparision study. Check in solvenet...
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    What happens during tapeout?

    Re: tapeout It is a stage where you handover your chip design to the foundry like TSMC,UMC etc . You need to follow guidelines and fill the required data asked by the foundry. You have to make sure you design is clean in aspects like timing,DRC, LVS, Antena, Density, FIll before giving the...
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    respin a design with one metal layer less

    you might want to change the aspect ratio accordingly
  8. R

    Clock distribution and power routing

    high frequency power routing In general for high frequency designs we route the clock nets close to the power or ground nets to shield the clock tree from unwanted crosstalk effects.
  9. R

    help: how can I do in Astro follow with 0.13um process

    Hi, There Astro usage wont differ much provided u r using the correct technology data (tf, itf for tluplus) for the respective tehcnology. Once difference I remember is the notch fill methadology which is different in 130 and 180 in Astro. As newcpu told we should consider SI when Implementing...
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    GDS Straming in issue

    Hi, I am having problems streaming in GDS files of Custom Analog blocks from Cadence Virtuso into Synopsys Astro.Only the layers matching in both the tech files of being streamed in properly and others are missing. Did anyone face this problem. Do you have a gdsInLayer.map file for the Cadence...
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    Shift from SW to Chip designing

    Hi Biswami, My honest advice is to follow your dream.I am telling this bcoz you shouldnt be in a position where 10 years down the lane you keep regretting for what you should have done early. I guess you are having enough time to switch to ASIC Design I did my PGDiploma in Sandeepani and I...
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    What is the significance of preserving hierarchy in Astro?

    Re: hierarchy designs It is important to preserve the hierarchy in Astro if you need a hierarchial verilog out. When you select the preserve hierarchy the Astro will initiate the Common Graph which keeps tracking the hierarchial boundaries when the implemnetation is goiong on. When you want...
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    How do we connect all VDD, VSS to global VDD /VSS nets ?(aprPGConnect)

    aprpgconnect hi Prasad, You are right. The aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. For physical connection you can use the axgCreateStandardcellRails command to create the std cell rails and through them connect to the rings or the straps depending...
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    Handle spare gates in Astro ??

    astsetdonttouch #t You can can use the astSetDontTouch attribute the spare gates.
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    drc in semi-custom design

    Hi Siva, While doing semi-custom design the last thing, you want to have is DRC inside standard cells, bcoz u cant do much to clear them. By the way which std cell library are you using. Contact the nendor and get it right
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    Chip will not work above 600MHz without decap cell in core?

    core decap cells Having decap cells for designs working at higher freq is essential bcoz, without decap cells the power delivery network can supply power instantaniously to gates all over place having high switching bcoz of higher freq. Hope it helps
  17. R

    placeable area violations after routing

    Hi Pradeep, I am not sure why u r doing the filler cell insertion before routing. What is the utilization of ur design bfore placing the filler cells.
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    Synopsys .lib generation help

    .lib file synopsys For all my digital blocks I am having .lib coming from the vendors. I am having some custom IOs in the design. These custom IO are similar to the regualr TSMC IOs but have some extra pins(pins cap is available) .I want to create .lib for these so that I can give pin cap...
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    regarding si analysis

    Hi Sivakumar, Glitch is a small blip which occurs when the difference in data arrival times at the input pins is more than the delay propogation of the gate. As u told noise is a result of capacitive coupling between nets. Hope this helps. Rgds, Rakesh
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    Synopsys .lib generation help

    synopsys liberty Hi spauls, In dont have encounter as in my company we have Synopsys flow and I want to use the .libs in Astro, not generate using Astro

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