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    question regarding timing analysis or slack time

    Hello everyone. Currently, Im designing a processing element. This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484. I have problem on the timing analysis. The is no setup time and hold time reported as shown below. There is no slack for setup time and...
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    Timing analysis guidance

    Hi all. Im using Xilinx ISE Design Suite 14.7 for my timing analysis using a constraint shown below. After PAR there were errors on the timing analysis based on the timing constraint above. Below shows some of the error example I need help and guidance based on the experience to improve...
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    Xilinx XPower Analyzer Confidence Level

    Hello everyone. Im using ISE Design Suite 14.7 and Xilinx XPower Analyzer to find the total power for my design. 1. I notice that both the design nets matched and simulation nets matched is not 100%. Why is that? 2. What can be done to increase the confidence level? 3. One more thing, based...
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    Generating SAIF file

    Hello everyone. Im wanted to generate the SAIF file from ISIM. Im using Xilinx ISE Design Suite 14.7 Ive found the method to generate SAIF file. Please also refer to the attach figure. However, there is an error. Please help me to solve the error or any other method to generate SAIF...
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    [SOLVED] writing to a text file

    Dear all, How can I write the displayed output in the command prompt to a text file? #include<stdio.h> #include<string.h> int main() { /*declare and initialise variable*/ char message[32][114],buffer[114]; int i=1; FILE *file_in; FILE...
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    wrting multiple substring in multiple text file

    Hello. Im writing a C programme that reads the files and trying the save the processed string to other file. So the string is: The inital coding is: #include<stdio.h> #include<string.h> int main() { /*declare and initialise variable*/ char...
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    Weird synthesis error (Xilinx, Verilog)

    Dear all. Im currently synthesizing a design using Xilinx ISE. 14.7 Based on the warning below, it says that ALL the sub module is unconnected. WARNING:Xst:1290 - Hierarchical block <CompInterA> is unconnected in block <A>. It will be removed from the design. WARNING:Xst:1290 - Hierarchical...
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    timing on design compiler

    Hi everyone. From what I know, critical path is the longest path between two flip-flops in a design. However, based on the timing report, the critical is not between two flip-flops. Can someone please explain to me why is that? Does ACIS and FPGAs have different critical path definition...
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    Error to run waveform

    Hi everyone. I have a problem to run waveform using vcs command for synopsys. Here is the details recompiling module DNASeqSynopsys_tb because: Generated file (Pz2Jf) not found, or not incremental. recompiling module ProcessingElement because: Generated file (ipNEp) not found, or not...
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    Design Vision Power Report analysis

    Hi everyone. This is my power report from Design Compiler. **************************************** Report : power -analysis_effort low Design : ProcessingElement Version: J-2014.09-SP2 Date : Mon Feb 26 08:44:25 2018 **************************************** Library(s) Used...
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    Fixing LVS Errors in Synopsys IC Compiler

    Hi everyone. How can I fix these LVS errors? -- LVS START : -- Total area error in layer 0 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 1 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total area error in layer 2 is 0. Elapsed = 0:00:00, CPU = 0:00:00 Total...
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    IC Compiler error for clock tree synthesis

    Hi all. Based on the log report below, I dont unserstand why there is error during clock tree synthesis? icc_shell> clock_opt Warning: Starting from the 2011.09-SP4 release, clock_opt will NOT perform congestion-driven placement by default. (PSYN-1111) The options for clock_opt...
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    [SOLVED] Synopsys IC Compiler warning and Error

    Hi all, I get this warning when I run IC Compiler in Synopsys. These are some of the errors that I get. What does it mean? I dont really understand.

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