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  1. J

    VHDL or Verilog - Which way to go?

    I have an option to choose between Verilog and VHDL to implement logic gates for now. I have checked around, but do not understand what people mean by saying that VDHL is verbose and Verilog is not. I had also read that VHDL is "very deterministic" and Verilog is "only deterministic if you...
  2. J

    Job prospectus

    I would like to know the job prospects if I choose antenna design for my graduate studies? Sorry if this is the wrong place to discuss this. Thanks.
  3. J

    [Moved]: Model parameter values

    sry im very new to this. i could'nt find the pdk for a finfet from the link u provided. any link to a pdf or other doc that states parameter values like fin height, length of gate etc. would be much appreciated. (ive been trying for days, without any success :/)
  4. J

    [Moved]: Model parameter values

    Im workinh with BSIM CMG in ADS. Does anyone know how to get the industry parameter values?
  5. J

    [SOLVED] FinFET model for ADS

    i figured level 72 is not compatible with the 2011 version. hoping ads 2014 will solve this issue.
  6. J

    [SOLVED] FinFET model for ADS

    I need a FinFET model to perform my simulations on, in ADS. I tried importing the 7nm PTM_MG (LSTP NMOS) into ADS. However, I get a warning stating that level 72 (which is the level specified in the .pm file for nmos) is invalid and hence ignores the line. I am a new user to both ADS and HSPICE...

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