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    conditional ifdef for multiple projects ?

    Hello All, Can some one please help me with this issue. I have 3 different projects A1, A2, A3 and i am using ifdefs. Can someone tell me a way to avoid such scenario ifdef A1 <code1> elsif A2 <code2> elseif A3 <code3> endif code1 and code2 are same, i dont want to use ifndef . So can...
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    Help with ASIC projects

    asic projects Hi All, I need to design a project spec for a course. The course needs a design project which requires verilog. The verilog code is to be synthesized using cadence. Can some one suggest me good projects or some ideas on which I can design the spec on. Thank you

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